Data Prefetch Logic – What is it Worth?

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Memory Benchmarks

In order to determine whether bandwidth issues would limit the ability of the Data Prefetch logic to ‘work its magic’, I ran several memory specific diagnostics. The most important one is STREAM, which attempts to determine the highest bandwidth utilized in an application that simply streams data through the memory subsystem as fast as possible. I specified 10 iterations for each stream run to get the best score possible.

As can be seen here, none of these tests even comes close to reaching the maximum theoretical bandwidth of the GTL+ bus, and in fact, don’t even reach 50% of it. It also shows that the Celeron T and PIII Coppermine, both running at 100MHz FSB, get almost identical scores, while the PIII T gets significantly higher bandwidth utilization than the PIII Copermine running at 133MHz FSB. Data Prefetch logic in action! Of course, this is a synthetic test, so it only shows the maximum potential benefit of the feature, not the typical benefit. Still, almost a 30% improvement is quite impressive for one little feature.

Another benchmark that looks interesting is PCMark2002. The memory tests seem to isolate the speed of memory and cache, but the Block Read numbers here seem awfully high – very close to the theoretical bandwidth of the bus. I will be interested in hearing feedback about the throughput shown here (is it possible to shove this much data across the bus?). The jury is still out as to whether this is a valid benchmark for comparing across platforms, but a comparison of these architecturally similar processors yields some interesting results. I specified 10 iterations of the tests selected, and PCMark2002 presents an average score for the 10 runs. The numbers presented here are all in MB/s.

The first strange thing to notice is that the Coppermine part running at 133MHz FSB gets a higher throughput in the non-cached tests (above 256KB blocks) than the Tualatin part, so either there is something odd about this particular test (and benchmark) or the Data Prefetch logic is actually detrimental in this circumstance. Obviously more research and discussion is necessary here. As can be seen in all of the ‘small block’ tests (under 256KB), the L1 cache speeds are almost identical, but once again the Coppermine seems to have a slight advantage in L2 speed. Obviously the Data Prefetch logic will have no impact when data is accessed from cache, but it does appear that L2 cache is a bit slower on the Tualatin parts.

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