E2k Instruction Set: Complex and Variable Length
The E2k uses a variable length VLIW instruction encoding. An instruction consists of 2 to 16 ‘syllables’, each of which is 32 bits long. The first syllable encodes the length of the instruction as well as information about the presence and number of optional syllable fields in the rest of the instruction. This scheme is shown in Figure 2.
Figure 3. Minimum and maximum length E2k VLIW Instructions
An E2k instruction can include up to six ALU syllables (instructions to each of the six ALUs), up to three prepare to branch syllables, and up to two syllables to specify additional extended ALU operations for chained sequences of operations. The E2k instruction can also include up to four syllables of move instructions to direct data from the prefetch buffer to the register file(s), and up to the same number of immediate data symbols. In addition, there can be up to three symbols each of predicate logic calculations, and predicate and execution unit mask. If you add up the maximum number of syllables for each function mentioned you will get 26, which is more than the maximum 16, so apparently not all combinations of syllables can be used. This ISA non-orthogonality can complicate the task of code generation within the compiler.
The E2k instruction format is much more complex than existing examples of variable length VLIW instruction sets such as Intel IA-64, Sun MAJC, and TI C62xx. Like the CISC x86, an E2k instruction word must be partially analyzed before its length and composition can be determined. In addition, the routing of instruction information to various functional units is made more complex, because the exact location of fields within the instruction word can vary depending on the presence and number of optional classes of syllables. The presence of field multiplexors and their associated control logic in the instruction path adds complexity and delay to the processor logic, which can lead to slower critical paths or extra pipeline stage (such as the scatter pipe stage, number 3 in Figure 2), compared to RISC processor implementations. Perhaps a new architecture category, VLI-CISC, is needed to encompass the E2k.
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