The Revolution Above
While the x86 architecture was gradually improving in the 1980s, the larger world of computing was being turned upside down by the RISC revolution in thinking about computer architecture design. Instruction set architectures with massive commercial success and widespread presence in the mid range of computers, like the VAX and MC680x0, were swept away by new RISC-based architectures like SPARC, PA-RISC, and MIPS . Ironically the two computer market segments that proved impervious to the RISC tidal wave were the least expensive, PCs, and among the most expensive, IBM compatible mainframes. Both PCs and mainframes shared several similarities in the 1980s that protected them. Both had large, valuable software bases that were effectively non-portable due to the extensive use of assembly language programming. In contrast the mid range of computers tended to use programs coded in high level computer languages which ran on portable operating systems like Unix.
The second similarity between PCs and mainframes was that specific design concerns unique to each class of computer mattered more than the huge CPU performance and cost/performance advantages offered by RISC based processor design. For mainframes the overriding hardware concerns were summarized in the catch phrase acronym RAS (reliability, availability, serviceability). Performance concerns primarily centered around I/O capacity and mass storage devices rather than the CPU. In the case of the PC, cost was the overriding design goal and x86 MPUs held a huge advantage due to being made in much higher quantities than any individual RISC device or family. The cost of a complex and difficult to design integrated circuit like a MPU is strongly influenced by manufacturing volume. Because of this x86 processors were priced in the hundreds of dollars while RISC processors cost thousands of dollars. CPU performance, to the extent that it was important in a 1980s era PCs, focused on manipulation of integer and character data rather than the floating point computation that most RISC processors particularly excelled at. The graphics display capabilities of these PCs were very primitive and 3D graphics intensive applications like games and PC-based technical applications which demand great FP performance still lay a decade in the future.
Despite the difference in cost structure between PCs and RISC based workstations in the late 1980s and early 1990s Intel still perceived a threat from above. In particular, Sun Microsystems was making rapid strides in growing a valuable user base as well as bringing down the cost structure for RISC desktop machines with highly integrated processors like the MicroSPARC. There was even talk among some industry analysts of Sun directly taking on the PC with a “SPARCintosh”, a hypothetical inexpensive Unix workstation with a user friendly graphics interface. Perhaps to head off this threat (the best defense is a good offense), or perhaps to expand into more lucrative markets, Intel came up with a technical answer to encroachment by RISC – the Pentium Pro.
The Pentium Pro was the first x86 implementation to use the now familiar scheme of decoupled execution in which an in order front end fetched x86 instructions and broke them down into one or more simpler and easier to handle primitive instructions called micro operations or uOPs) for execution by an out of order superscalar back end. This innovative new microarchitecture was also given a boost in the form of a custom high speed 256 KB L2 cache device that was packaged along with the MPU device in a multi chip module (MCM) package and communicated with it over a high speed dedicated bus internal to the package. The final kicker was that Intel was able to bring out the Pentium Pro in 0.35 um technology before any of its RISC competitors. The surprisingly strong performance of the Pentium Pro  sent shock waves through the computer industry and most RISC vendors realized they would never be able to achieve the critical combination of cost parity and performance advantage sufficient to replace the Intel x86 in personal computers despite the x86’s multitude of architectural shortcomings (lack of GPRs, complex serial instruction encoding, failure to separate memory access and computation, stack oriented FP architecture, status flag based conditional instructions, support for self-modifying code etc.).
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