Can Intel Transmute Big Iron to Desktop Gold?
It should be obvious by now that current reality makes it virtually impossible for another MPU vendor to challenge Intel backed x86 on the desktop with a different ISA. No other chip maker comes close to its manufacturing and design capacity, wealth, and influence with independent software vendors (ISVs) and hardware OEMs. The interesting question that naturally arises is whether Intel itself could replace x86 with a different architecture if it chooses. Or has x86 taken on a life of itself beyond the control of its creator similar to how the Wintel PC standard escaped the grasp of mighty IBM? This is an increasingly important question because many industry observers are convinced Intel will eventually attempt to replace x86 with the Itanium processor family, first in servers, then on the desktop, and eventually in compute intensive mobile applications.
Intel openly positions IPF against RISC based rivals in the mid to high end server market. The fact that Intel has not yet publicly disclosed plans for a 64 bit addressing extension for its Xeon family of x86 server MPUs seems to indicate that IPF will also increasingly compete with Xeon in lower end server applications as the need for large virtual and physical address spaces migrates downwards. Although the eventual need for 64 bit addressing on the desktop has long been predicted, often prematurely , the subject is currently at the center of a lot of nonsensical claims and hype from enthusiast supporters of AMD’s rival 64 bit extension to x86 and potential IPF competitor. Nevertheless, these claims are only unreasonable by their accelerated time scale, not by being ultimately incorrect. It is easy to make a compelling argument that 64 bit logical addressing capability will become increasingly useful, perhaps even necessary, for mainstream desktop hardware and software within the next five years.
The impressive die size and power consumption of current IPF processors makes them unsuitable for desktop use but this situation is a function of their 0.18 µm processing and the intended market. For example, the die size and maximum power consumption of the Itanium 2 processor (421 mm2, 130W) are comparable to the Alpha EV7 (397 mm2, 125W) and POWER4 (415 mm2, 115W), two other 0.18 µm high end server MPUs. Upon closer examination, the Itanium 2 CPU core (processor logic plus first level caches) is actually about 20% smaller in area than that of a Pentium 4 made in the same 0.18 µm process and uses about half the number of transistors. Removing the x86 compatibility logic shrinks the Itanium 2 core to about 70% of the size of the Willamette CPU and significantly widens the complexity gulf. Ironically this change could also substantially raise the performance of IPF processors running x86 legacy applications by forcing a switch to a software based x86 compatibility scheme similar to DEC’s FX!32 or Transmeta’s code morphing software .
In terms of addressing the desktop class form factor, the 0.13 µm Madison/Deerfield  version of Itanium 2 can reportedly operate at 1.3 GHz while keeping maximum power dissipation comparable to a 2.66 GHz Northwood Pentium 4. In this scenario the IPF processor would provide roughly 10% higher integer performance and about twice the floating point performance for native applications. Advances in compiler technology  and processor implementation techniques  will very likely proceed at a much faster pace for IPF than x86, a CISC architecture nearly two decades older, so this gap will tend to widen over time, especially with growing ISV experience optimizing for the architecture . However, because of code density driven differences in minimum effective cache sizes for x86 and IPF desktop processors, it is unlikely that their variable manufacturing cost could cross until both employ 90 nm or better process technology. That means 2005 at the earliest according to Intel’s current public roadmap for IPF.
The software side of the equation is more problematic given the current paucity of native IPF applications and the only recent introduction of a production ready IPF version of the Windows operating system. To replace x86 with IPF, Intel would be faced with the classic chicken-and-egg dilemma in convincing ISVs to create native IPF desktop applications for a non-existent desktop user base while convincing users to buy IPF desktop systems to run non-existent native IPF desktop applications. Intel would likely attempt to solve this dilemma on the software availability side by offering substantial financial support and incentives to ISVs. In contrast, AMD can potentially sidestep this dilemma on the hardware demand side with AMD64 by offering 64 bit capable MPUs that also run existing x86 software competitively in both performance and price. Fortunately for Intel, Microsoft will likely strongly support IPF regardless of whether or not Intel expands IPF’s reach to encompass the desktop. IPF is the only merchant MPU family that can credibly offer Microsoft access to corporate enterprise level computing, the so-called glass cathedrals, a goal it has eagerly sought for years.
Even if the hardware and software pieces fall into place, what would motivate Intel to attempt to replace x86 with IPF? Such a move would allow it to consolidate its product lines while marginalizing competitors in both the desktop and in large scale systems. This move also frees Intel of the need to extend the x86 ISA to 64 bits and design increasingly complex, expensive, and error prone processor implementations to extract ever higher levels of performance from an inherently awkward and stubbornly low ILP ISA. It is not hard for critics to invoke frightening Tolkien style imagery of a malevolent Intel carefully crafting and positioning IPF as “one architecture to rule them all”. Indeed, it is likely that no other company would be able to build and sell IPF compatible MPUs for many years with all the legal and technical hurdles to overcome. Regardless of how undesirable such an outcome is from a competitive point of view, it is obvious that the exponentially rising cost of state of the art semiconductor manufacturing capacity will ultimately drive consolidation in the high end MPU market regardless of processor architecture.
What could IPF potentially offer desktop users several years from now that x86 can’t provide? Ignore the issue of 64 bit logical addressing for a moment as AMD has demonstrated it is an artificial barrier for x86. For the equivalent cost, power dissipation, and design aggressiveness in 90 nm process technology, an IPF desktop MPU might provide 10 to 30% higher general purpose/integer performance and perhaps double the floating point and DSP capabilities of any x86 or AMD64 processor. Given the type of technical and recreational applications that drives much of the sales of high end desktop computers today this combination may prove a powerful incentive for both software developers and users.
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