Escape From the Planet of x86

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Conclusion: At Best a Long Goodbye

Every military analyst knows that it is far easier to assess the technical and operational capabilities of a secretive entity than its intentions. Intel likely has plans for a number of contingencies, and the replacement of x86 is undoubtedly one them. But if Intel does decide to replace x86 on the desktop with IPF, and the technical scenario I have painted proves accurate, the overwhelming presence of x86 in desktop computing would not start to diminish until 2005 at the earliest and would remain significant during a long period of overlap, perhaps extending even into the next decade.

Most mainstream uses of PCs have long ceased to be limited by processor performance and buying decisions by individuals are often determined by marketing and price while institutional purchases are typically driven by vendor relationships and price. Similarly most desktop class applications will continue to run comfortably in a sub 4 GB address space for a very long time if not indefinitely. This poses a potential second chicken-and-egg dilemma for Intel in replace x86 with IPF – mainstream adoption will be price sensitive but costs of IPF MPUs will fall naturally only by mainstream adoption driving up volumes. Intel may have to employ aggressive forward pricing in combination with a clever marketing campaign to push IPF beyond the performance sensitive minority among PC buyers and over the top.

For all the technical and manufacturing leverage Intel holds over the computer industry it is at best like the captain of a supertanker cruising at full steam – nominally in control but strongly limited by inexorable natural laws of inertia. A decision to make a major change in direction may be taken quickly but its implementation will take time and the monstrous vessel will cover quite a distance in the original direction while change occurs. Even if Intel has taken the decision to ultimately replace x86 with IPF, it obviously recognizes the gradual nature of architectural change in the computer industry as it is still going full steam ahead with development of multiple new generations of x86 processors.

References

[1] “the 8086 Family User’s Manual”, Intel Corporation, October 1979.

[2] Weiss, R., “RISC Takes Gold in Processor Olympics”, Computer Design, November 1996, pp. 61-78.

[3] Bhandarkar, D. and Ding, J., “Performance Characterization of the Pentium Pro Processor”, Symposium on High Performance Computer Architecture, Feb 1997.

[4] Hof, R. et al, “MIPS Computer Has a Beautiful Future Behind It”, Business Week, October 17, 1991, P. 52.

[5] Kelly, R., “MIPS Dips: Chip Too Risky?”, Informationweek, May 11, 1992, p. 34.

[6] Thompson, J. and Ryan, M., “Apple, IBM Ink Formal Alliance Plan”, Electronic Engineering Times, October 7, 1991.

[7] Hayes, M., “Mac Clone Outpaces Macintosh”, Informationweek, November 6, 1995, p. 18.

[8] Sager, I. Et al., “Time May Have Passed PowerPC By”, Business Week, March 4, 1996, p. 72.

[9] Jain, A. et al, “1.38 cm2 550 MHz with Multimedia Extensions”, ISSCC 1997 Digest of Technical Papers, p. 174.

[10] Turley, J., “Alpha Runs x86 Code with FX!32”, Microprocessor Report, Vol. 10, No. 3, March 5, 1996, pp. 11-13.

[11] Hookway, R. and Herdeg, M., “DIGITAL FX!32: Combining Emulation and Binary Translation”, DIGITAL Technical Journal, August 28, 1997.

[12] Judge, P., “Digital’s Struggle to Save its Alpha Chip”, Business Week, December 30, 1996, p. 44.

[13] Mashey, J., “64-bit Computing”, Byte, September 1991, p. 135.

[14] Halfhill, T., “Transmeta Breaks x86 Low-power Barrier”, Microprocessor Report, Vol. 14, Archive 2, February 2000, p. 1.

[15] Ohr, S., “Pumped-up Itanium will debut at ISSCC, Electronic Engineering Times, February 10, 2003, p. 1.

[16] Winkel, S., “Optimal Global Scheduling for Itanium Processor Family”, EPIC-2, November 18, 2002.

[17] Adl-Tabatabai, A. et al, “The StarJIT Compiler: A Dynamic Compiler For Managed Runtime Environments”, Intel Technical Journal, Vol. 7, Issue 1, Februrary 19, 2003, pp. 19-31.

[18] Arnold, R. et al, “Reducing the Cost of Large Register Files in EPIC Architectures with Stacked Register Aliasing”, EPIC-2, November 18, 2002.

[19] Choi, Y. et al, “Design and Experience: Using the Intel Itanium 2 Processor Performance Monitoring Unit to Implement Feedback Optimizations”, EPIC-2, November 18, 2002.


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