The Spider and the Mountain

Pages: 1 2 3 4 5 6 7 8

A Tale of Two Chips

The annual International Solid State Circuits Conference is the forum that chip design teams have traditionally used to disclose detailed information about their latest and greatest technical feats. These accomplishments range across a spectrum of technologies and applications, from dynamic and flash memories to exotic analog and radio frequency devices. But for microprocessor enthusiasts, the 2002 edition of ISSCC will likely be best remembered for two high-end 64-bit chips, the Compaq Alpha EV8 and the Intel second generation Itanium better known by its code name McKinley. These two remarkable processor designs are, in many ways, studies in contrast. They differ starkly in instruction set architecture design philosophy, implementation philosophy, process technology, their stage in the development cycle, and their ultimate destiny.

The McKinley, officially referred to as the “next generation Itanium processor”, is a second generation implementation of Intel and HP’s controversial IA64 instruction set architecture rendered in a 0.18 um bulk CMOS process with aluminum interconnect. It reached the milestone of first silicon more than a year ago in good enough shape to boot a variety of operating systems. After the long verification and characterization process common to all high end server processors the McKinley entered pilot commercial production in 4Q01. Products based on the McKinley processor will likely be officially released within the next three months. Perhaps to help make up for the embarrassing withdrawal of their McKinley paper from last year’s ISSCC, Intel and HP presented no less than six papers this year describing many aspects of the design in great detail.

The EV8, previously covered in a three part series (Part 1, Part 2, Part 3), was a fourth generation Alpha processor core that targeted a 0.13 um SOI CMOS process with copper interconnect. Not only was it the widest, deepest, and most lavishly equipped out-of-order superscalar processor design ever attempted, it also aggressively targeted thread level parallelism with support for four way simultaneous multi-threading (SMT). Unfortunately Compaq canceled this project last June, more than a year before first silicon was planned. Nevertheless, the fact that a dead “paper” design was presented at ISSCC at all is a measure of the technical community’s wide spread interest in the EV8 as well as the general expectations of new and innovative approaches to high performance processor implementation that have historically accompanied major disclosures from the Alpha design team. Ironically the former EV8 team is still nearly intact but now works for Intel designing future products in the IA64 family.

Pages:   1 2 3 4 5 6 7 8  Next »

Be the first to discuss this article!