The Spider and the Mountain

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The defunct Alpha EV8 design was arguably the most aggressive and ambitious high end microprocessor design ever publicly disclosed. Had it been completed and functioned as its designers intended, and brought to market within a reasonable time frame, it would have likely taken the performance leadership crown against all contenders, as had three previous generations of Alpha microprocessors. Although the EV7 should prove to be an outstanding technical success, and possibly even a minor commercial one too, it will forever stand in the shadow of the EV8 and Compaq’s decision to trap the Arana in a corporate web of intrigue and quickly and quietly kill it.

In contrast to the EV8’s cold grave, the McKinley seems to have a bright future ahead of it. Unlike the execrable Merced, the second generation IA64 processor is a well designed chip with an incredibly capable on-chip cache hierarchy. That cache hierarchy, combined with many other measures to minimize instruction execution latency as well as increase the clock rate, should help McKinley overcome the burden of an ill-conceived and misguided instruction set architecture to yield respectable integer and floating point performance levels. By offering decent high end performance at relatively low costs (from its chip merchant business model and potential economies of scale), Intel and its business partners will likely see strong customer acceptance when it officially releases McKinley later this year. Perhaps enough to turn the corner and start paying a return on the billions invested in IA64 over the past eight years.


[1] Preston, R. et al., “Design of an 8-wide Superscalar RISC Microprocessor with Simultaneous Multithreading”, Digest of Technical Papers, 2002 IEEE International Solid-State Circuits Conference, p. 334.

[2] Naffziger, S. and Hammond, G., “The Implementation of the Next-Generation 64b Itanium Microprocessor”, Digest of Technical Papers, 2002 IEEE International Solid-State Circuits Conference, p. 344.

[3] Smith, S., “Intel Architecture: Features & Futures”, Proceedings of Microprocessor Forum 1998, October 1998, MicroDesign Resources.

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