Moderated Discussions

Expand Threads:
View Last:
Highlight Last:
Start New Thread
TopicPosted ByDate
8086 MOV SS / POP SS interrupt delay... and x86 decoding in generalanonymou52022/11/26 04:38 PM
Is 1 more expensive than 0?Andrey2022/11/21 04:23 AM
posts disappear ?Michael S2022/11/16 12:41 AM
IEEE binary128 support on ARM Macs ?Michael S2022/11/14 03:18 PM
x64 successorAvantgarde2022/11/13 04:42 AM
Why is Rosetta 2 fast?Ungo2022/11/10 02:01 PM
One 512-bit vector unit versus 2 256-bit vector units, re Zen 4 AVX-512Jeffrey Bosboom2022/11/04 05:18 PM
A16 packaging---2022/10/25 09:45 AM
The Intel 2022-09 ISA ExtensionsAdrian2022/10/20 12:11 AM
How would undocummented, private ISA extensions work in Linux-based systems?Ana Rodriguez2022/10/19 10:12 AM
Any die shots of Ryzen 7000 I/O die?hobold2022/10/18 12:52 PM
Playing with fire? Shutting down the Chinese semiconductor industryRay2022/10/14 04:08 PM
downturnanonymou52022/10/12 11:23 AM
GPNPU?---2022/10/07 01:40 PM
ARM new developments 2022dmcq2022/10/07 05:50 AM
Pat Gelsinger interviewAdrian2022/10/07 04:17 AM
SPECworkstation 3Per Hesselgren2022/10/01 05:06 AM
NVIDIA Linux driver and Kernel 5.19 & 6.0Philippe2022/09/30 04:14 AM
ARM announces Armv8.9 and Armv9.4noko2022/09/29 07:02 PM
For Chester: Nvidia’s RTX 4090 Launch---2022/09/28 05:57 PM
Zen 4 idle power?anonymous22022/09/26 09:32 PM
Zen4's AVX512 Teardown (from 07:57 AM
A16 Jetstream2 result---2022/09/22 01:46 PM
Why no callee-saved vector registers?Michael S2022/09/20 12:44 PM
new versions of gcc on Debian LinuxMichael S2022/09/19 09:28 AM
GH repo to measure core-core latencyanonymous22022/09/18 01:40 PM
ARM Neoverse V2 - SVE2 is 4x128anonymous22022/09/16 08:04 AM
Connectivity issues?Doug S2022/09/15 07:52 PM
Data integrity of L1 cachesanon22022/09/15 06:04 PM
What implemention of TSX is present on Sapphire Rapids?Robert Williams2022/09/12 06:58 PM
A packaging question---2022/09/11 08:28 PM
No Perf/Clock gains on A16_2022/09/08 03:27 PM
forum buganonymou52022/09/01 12:22 AM
Arm sues over Nuvia/Qualcomm acquisitionWes Felter2022/08/31 02:06 PM
New details on NVidia's Grace server CPUJeff McWilliams2022/08/31 11:20 AM
Zen 4, AVX-512 support, 2 cycle execution timeanonymous22022/08/29 04:08 PM
Chips & Cheese analyzes Tachyum’s Revised Prodigy ArchitectureNobod2022/08/27 08:21 AM
Do we need branch prediction?Kara2022/08/24 01:07 PM
Hardware Transactional Memory, the end?rwessel2022/08/20 05:50 PM
What happened to mill computing? (NT)Kara2022/08/20 01:29 PM
Zen 4 I/O Die at 6nmanonymous22022/08/18 02:56 PM
Qualcomm's second server act, after Centriq cancellationBeastian2022/08/18 10:43 AM
Intel's abandoned Pentium 5 projecttacobell2022/08/14 12:35 PM
Zen 4 Infinity Fabric clock reaches 3 GHzWes Felter2022/08/09 12:40 PM
AEPIC leakAdrian2022/08/09 11:21 AM
Interesting ARM compiler data---2022/08/08 01:54 PM
ISA (x86/armv8) q: Why isn't "gcc -Os" ~ "gcc -O3" ? (NT)anonymous22022/08/05 09:11 AM
Tachyum sues Cadence over IP "sabotage"Wes Felter2022/08/03 02:17 PM
Empirical data on ISA design parametersNvaxPlus2022/08/02 07:45 AM
What kind of FPGA is this?Per Hesselgren2022/07/31 07:48 AM
AMD passes Intel in market capanonymous22022/07/29 04:47 PM
RIP Optane/XPointWes Felter2022/07/28 06:53 PM
Code density comparisonsRayla2022/07/27 12:44 PM
CheriBSD running KDEdmcq2022/07/26 02:32 PM
IBM 5 bit microcontrollerDuane Sand2022/07/24 10:50 AM
Happy 26th anniversary!David Kanter2022/07/23 06:24 PM
China’s SMIC Is Shipping 7nmSomata2022/07/21 01:52 PM
Microinstruction format in older Atom CPUsAdrian2022/07/19 03:57 AM
Imagination TechnologiesMr. Camel2022/07/15 10:17 AM
Retbleedanonymous22022/07/13 02:14 PM
[OT] Sturgeon's Observation: reasons for its truth?Paul A. Clayton2022/07/10 04:20 AM
Is SVE really Apple's future?---2022/07/09 03:07 PM
Shape of largest die that fits on reticleMath Nerd2022/07/08 03:57 AM
Linear Address Spaces: Unsafe at any speed [article]Kester L2022/06/29 12:49 PM
New ARM Cortex cores launchRayla2022/06/28 07:49 AM
EPYC3 refuses to boostMichael S2022/06/28 02:44 AM
TSMC's node densities - new article from AngstronomicsBjörn Ragnar Björnsson2022/06/27 11:52 AM
NDA balderdash, Arm guessing gameKara2022/06/26 09:55 AM
forget transistor size, we're lacking architectsKara2022/06/26 09:17 AM
Apple memory compression --2022/06/25 12:39 PM
OK dumb question timeDoug S2022/06/24 12:31 PM
Wider vectors vs GPU---2022/06/24 08:43 AM
ARM refresh MIA?Rayla2022/06/21 09:59 AM
P6 High Performance I/O and WebMr. Camel2022/06/21 05:39 AM
ILP wall vs SIMD vec2022/06/17 11:44 AM
M2 benchmarks-2022/06/15 11:27 AM
Measuring latency on Snapdragon devicesJonathan Kang2022/06/14 10:47 AM
New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/12 06:05 PM
Zen 4 mobile (Phoenix Point) "chiplet architecture"AngstromAndy2022/06/10 03:46 PM
Pointer authentication flaw in M1Doug S2022/06/10 10:52 AM
Bone of contention: AMD resurrects AVX-512 ... sort of ...Björn Ragnar Björnsson2022/06/09 06:00 PM
Chips, Cheese and Sunny CoveJames2022/06/07 04:57 AM
macOS 13 virtualization framework to support Rosetta 2 inside Linux VMsUngo2022/06/07 12:36 AM
Peter Lewis = AIanonymou52022/06/06 04:57 PM
Apple unveils M2, taking the breakthrough performance and capabilities of M1 even furtherM22022/06/06 11:07 AM
GPU Using LPDDR5Someone with gray hair2022/06/03 11:36 AM
Crazy CXL NamesPeter Lewis2022/05/30 02:54 PM
[Fun] Transform any text into a patent applicationdmcq2022/05/29 01:25 AM
Intel Falcon Shores = Xeon CPU + Ponte Vecchio GPU + cache chipJohn R2022/05/27 11:25 AM
Performance of H100 SXM vs H100 PCIeMatt Hughes2022/05/27 02:17 AM
Zen 4 is really badKara2022/05/26 12:52 AM
Addressing in a NoC---2022/05/17 10:02 PM
EPYC Instinct ModuleJim Wilson2022/05/12 05:13 PM
Cache-Coherent Interfaces for High-end GPUsJim Wilson2022/05/12 04:43 PM
Apple's AVX512---2022/05/11 11:32 PM
display "equalization"---2022/05/09 06:30 PM
HD vs HP Process---2022/05/05 11:08 AM
Side-channel attacks on the data memory-dependent prefetchers in M1ribit2022/05/01 06:00 AM
DDR4 & DDR5, new Intel & AMD CPUsBjörn Ragnar Björnsson2022/04/29 06:20 PM
What's causing 5800X3D to perform much better on simulators than other "applications"?John H2022/04/27 04:20 PM
How maxOS manages M1 CPU coresAndrew Clough2022/04/25 04:11 AM
OpenBSD 7.1 is out for Apple M1Brett2022/04/23 10:21 AM
For fans of Minority Report UI's---2022/04/21 11:35 AM
Apple NVM machine---2022/04/19 03:52 PM
vGPUs?---2022/04/15 06:32 PM
Why was enterprise SATA SSDs common for a long time?Yuhong Bao2022/04/15 04:06 AM
Apple M1 TLB tradeoff anonymous22022/04/14 07:39 AM
VLM (on Compaq Alpha) would have been better than AWE...Yuhong Bao2022/04/14 02:20 AM
manufacturing/packaging of the M1 Ultra---2022/04/10 10:26 AM
Intel directly copies Zen presentation for Ocean Cove patentphoson2022/04/06 07:03 AM
IBM z16 Announcementrwessel2022/04/05 05:31 PM
SRAM vs logic scaling with mfg processes - temporary situation, not a real trendHeikki Kultala2022/03/28 10:15 PM
Centaur CNS analysisAdrian2022/03/23 01:18 AM
Page File SizesZenmont2022/03/22 05:39 PM
GPU Microarch DocsKyle Siefring2022/03/22 01:59 PM
Nvidia H100 Tensor Core GPUHopper2022/03/22 07:48 AM
M1 Ultra Chip Interconnect LatencyIan Ameline2022/03/16 12:22 PM
RISC-V asm instruction name madnessHeikki Kultala2022/03/09 12:35 AM
Apple M1 UltraWouter Tinus2022/03/08 11:20 AM
Intel to fuse-disable AVX-512 on Alder Lakeanonymous22022/03/04 02:26 PM
Optimizing blocksize of data based on memory architecturerocky2022/03/02 11:28 PM
Fujitsu announce discontinue mainframesBrett2022/02/26 12:59 PM
So the last shall be first...anon22022/02/23 07:25 AM
[738 words] Benchmarking interactive systemsPaul A. Clayton2022/02/21 07:51 AM
Exynos rnda sucks, but didn't everyone know that?Kara2022/02/20 05:57 PM
Intel to license x86 coresPaul A. Clayton2022/02/15 12:28 PM
AMD Tcase_max data Daniel B2022/02/12 04:26 PM
AMD acquiring XilinxKonrad Schwarz2022/02/11 03:21 AM
NVIDIA/Arm deal officially offrwessel2022/02/08 05:00 AM
Arm has released a prototype of its Morello development board for researchers at Google, Microsoft blaine2022/01/28 03:17 PM
Intel to build two fabs in OhioBrett2022/01/23 12:03 AM
*guaranteed* IO scheduling---2022/01/14 06:39 PM
Google TPU architecture evolution paperNet Random2022/01/07 09:26 AM
How good is Intel 7?anon22022/01/04 06:26 PM
A Critical Look at SVE2 For Integer Workloads-.-2022/01/02 04:56 PM
cache (non)banking---2021/12/26 10:07 PM
Apple CPU Perf/W. Main FactorKara2021/12/24 07:31 AM
NSO Group exploit emulates logic gates!Doug S2021/12/17 11:36 AM
Electricity is magnetismBrett2021/12/14 03:01 PM
Imagination tech back in cpu with risc-vKara2021/12/06 08:48 AM
Some info about the Amazon Graviton 3Adrian2021/12/03 05:51 AM
Cortex a710 merged core SVEKara2021/12/01 10:32 AM
Cost of rowhammer invulnerability?Chester2021/11/30 07:25 AM
Sectoring and suchlike in L1 caches---2021/11/29 09:03 PM
Integrated graphics card and discrete graphics card on Linux kernelPhil9955112021/11/26 05:29 PM
Where Walter Jeremiah Sanders III, AMD founder, ended up nowdays?anon2021/11/25 08:42 AM
Does Apple's M1 support BTI (branch target identification)?Gabriele Svelto2021/11/25 01:53 AM
Samsung to another build fab in Texas.Brett2021/11/24 02:55 PM
Forum search more broken than before?Michael S2021/11/18 01:34 PM
Top 500, x86 missing from top 4, Intel lagging AMDanonymous22021/11/18 11:17 AM
Scaling beyond saturationhobold2021/11/10 04:24 AM
Detailed investigation of M1 load and store bandwidths from L1 out to DRAM---2021/11/09 01:39 PM
The slow death of technical contentPaul A. Clayton2021/11/08 05:51 AM
Alder Lake, not bad, but not as good as expectedAdrian2021/11/04 05:56 AM
Run uarch-bench on ADLTravis Downs2021/10/28 11:30 AM
M1 Max as a renderer---2021/10/25 08:31 PM
Intel IDM 2.0Mr. Camel2021/10/24 03:44 AM
Yitian 710 anonymous22021/10/20 07:57 PM
GB5 Compute results for M1 Max---2021/10/20 12:08 PM
Apple's "chop" dieDoug S2021/10/19 07:29 AM
Introducing M1 Pro and M1 Max: the most powerful chips Apple has ever builtM1 Max2021/10/18 09:59 AM
Details on NVIDIA BlueField-3 Programmable Datapath Accelerator?Paul A. Clayton2021/10/12 11:17 AM
CMOS power vs. temperatureDaniel B2021/10/08 08:27 AM
Apple A15 L1D$Mr. Camel2021/10/07 10:43 AM
Strange data point on PC performanceEtienne Lorrain2021/10/06 05:38 AM
Nios V RISC-V soft coresGabriele Svelto2021/10/05 11:28 PM
Removed thread about linux kernel moduleDavid Kanter2021/09/27 11:26 AM
fab capacity or Why are there no GPUs (by Nvidia) to be had?Moritz2021/09/22 05:40 AM
Armv8.8-A and Armv9.3-Aanonymou52021/09/16 02:25 PM
Extra Apple M1 informationAdrian2021/09/15 11:52 PM
z14 and z15 cache latencies?David Kanter2021/09/12 09:40 PM
alder lake.inteluser2021/09/10 01:52 AM
POWER10 SAP SD benchmarkanon22021/09/06 02:36 PM
Apple and RISC-Vvvid2021/09/03 09:47 AM
Did IBM Just Preview The Future of Caches?Kester L2021/09/02 07:45 AM
AVX512 as co-processorMichael S2021/08/29 02:13 AM
IBM's AMX - Apple's wayMichael S2021/08/24 02:43 AM
Check out my tutorial at Hot ChipsDavid Kanter2021/08/22 10:40 AM
Tesla Project Dojo and InFO_SoWnemo2021/08/20 08:56 AM
Was Intel Holding Back?Jon2021/08/19 06:49 AM
Alder Lake: 1st Intel/AMD CPU with 6 instruction decodersAdrian2021/08/19 05:21 AM
Very-large superscalar execution without the costHugo Décharnes2021/08/18 09:34 AM
Post RISC Banked Register InstructionsBrett2021/08/15 11:38 PM
Split TLBsmatthew2021/08/07 09:21 AM
Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!Kester L2021/07/27 07:29 AM
AMX performance on M1 ?Michael S2021/07/27 02:01 AM
ARM Scalable Matrix Extensiondmcq2021/07/25 04:36 PM
Happy 25th anniversary RWTDavid Kanter2021/07/23 05:27 PM
Should variable symbols be "signed" with their length in bytes?Etienne Lorrain2021/07/23 01:40 AM
David – SNRanonymou52021/07/14 02:09 PM
inconsistent program state bug in Marvell Octeon TX2?Dummond D. Slow2021/07/12 02:12 PM
Is unsafe hell truly good for linux kernel in the future?cqwrteur2021/07/09 08:56 PM
Intel discontinued hybrid CPUsGionatan Danti2021/07/07 05:20 AM
High Bandwidth Memory on Xeon Sapphire RapidsJohn Clarke2021/07/03 06:01 PM
Intel to use TSMC 3nm anonymous22021/07/02 11:44 AM
Interesting ARM compatibility shim for Windows 11Beastian2021/07/01 01:48 PM
AMD EPYC Milan Review Part 2: Testing 8 to 64 Cores in a Production Platformanon2021/06/30 04:36 AM
Intel to disable TSX on (more) CPUsanonymous22021/06/28 01:54 PM
SiFive to provide its IP to Intel FoundryTriptych2021/06/22 06:24 AM
Intel Jasper Lake issue ratesIntelUser20002021/06/16 07:00 PM
component availability metadata2021/06/15 12:35 PM
Intel interested in acquiring SiFiveGabriele Svelto2021/06/11 12:50 AM
Google uses AI to design new chipsAndrey2021/06/10 01:20 PM
Cerebras intros wafer-scale systemanon2021/06/10 05:38 AM
AMD 3D VCache at end of year.Brett2021/06/01 12:00 PM
What's going on with the Arm A510 and Aarch 64?James2021/06/01 04:02 AM
M1RACLES (CVE-2021-30747) on Apple M1 siliconGionatan Danti2021/05/29 02:49 AM
Intel 10nm SF / Willow Cove now up to 5.3 GHz TVBJohn H2021/05/28 03:33 PM
(another?) upcoming self-hosted arm64 optionanonymous22021/05/25 11:40 AM
Ampere Altra Max 16MB LLC with 128 coresGanon2021/05/25 12:30 AM
On the RISC-V foundation's inability to ratify new thingsMylin Velodi2021/05/20 02:43 PM
Ampere switching to custom coreGionatan Danti2021/05/19 11:56 PM
Looks like Apple will be using chipletsDoug S2021/05/18 09:45 AM
A Case Against (Most) Context SwitchesLittle Horn2021/05/17 04:03 PM
Benefit of push/pop instructionsJörn Engel2021/05/17 11:39 AM
"AMD PCI Driver"Rob Thorpe2021/05/16 01:23 AM
How many physical registers are in an Intel CPU (NT)Paul2021/05/13 11:20 PM
Ice Lake energy efficiency regression?Daniel B2021/05/12 05:52 AM
LoongArchRayla2021/05/11 10:00 AM
IBM's "2nm" Gate-all-around - will it matter?David Kanter2021/05/10 05:26 PM
Post looking at BTB behavior and sizeTravis Downs2021/05/10 01:57 PM
4K pages probably used to be too largeYuhong Bao2021/05/01 12:01 PM
Leaking Secrets via Intel/AMD Micro-Op CachesAdrian2021/05/01 12:47 AM
Optimal pipelengthPer Hesselgren2021/04/29 08:44 AM
New details on ARM N2 and V1Andrew Clough2021/04/27 06:20 AM
M1 GPU register file sizeryu2021/04/23 03:11 AM
No ARM for NVIDIA?Marcus2021/04/19 05:23 AM
LoongArchLoongShot2021/04/16 02:01 PM
Nvidia Announces ARM HPC CPURayla2021/04/12 08:35 AM
Andre Seznec now at IntelJon Masters2021/04/12 06:53 AM
M1 uarch details Travis Downs2021/04/08 10:58 PM
AMD 5000 processors and PSFPhilippe2021/04/08 09:22 AM
Intel 3rd Gen Xeon Scalable (Ice Lake SP) Reviewanon2021/04/06 09:48 AM
Zen 3 Predictive Store ForwardingRobert Williams2021/04/03 03:33 PM
Please help to test strtod()Michael S2021/04/01 11:02 AM
It's pathetic, but Intel is looking to rename its 10nm as "7nm", 7nm as "5nm". Sadanon2021/03/30 08:40 PM
Armv9 officially announcedJon Masters2021/03/30 10:41 AM
How would you make a VCS for an EDA tool?Paul2021/03/28 07:14 AM
"Purchaser"-designed processors might facilitate asynchronous designPaul A. Clayton2021/03/26 07:22 AM
 Older >