Moderated DiscussionsExpand Threads:YesNoView Last:1 hour2 hours4 hours8 hours12 hours1 day2 days3 days5 days7 days14 days30 days60 daysAllHighlight Last:1 hour2 hours4 hours8 hours12 hours1 day2 days3 days5 days7 days14 days30 days60 daysAllStart New ThreadTopicPosted ByDateNYT on SPR---2023/01/26 09:37 AMDRAM error protection proposal for chips like M1 UltraMartin L.2023/01/22 08:16 AMhow to: 32-bit application on x86-64 LinuxMichael S2023/01/13 05:07 AMQ: DDR5 ECC memory speeds/timinganonymous22023/01/12 05:47 PM7950X3D, asymmetric cache?anonymous22023/01/05 11:48 PMHow ISA's scale, is x86 unbeatable?Kara2023/01/04 10:36 PMDavid Chisnall on RISC-V instruction space (and more)c2022/12/31 04:32 PMRISC-V core bugs?anonymous22022/12/29 05:07 PMZen 4 runs hot, is 4c going to be better?anonymous22022/12/22 01:42 PMtom's HARDWARE: Apple Is Struggling to Build Mac Pro Based on Its Own Silicon: Reportanonymou52022/12/20 01:55 AM(link) IEDM 2022: Did We Just Witness The Death Of SRAM?anonymous22022/12/14 02:27 PManandtech feels dead, chipsandcheese no better (NT)Kara2022/12/09 01:51 AMIntel not a monopoly any more:Brett2022/12/08 09:47 AMWhat happens when DRAM has more bandwidth than Layer 3 cache?Etienne2022/12/08 06:20 AMAny thoughts on Dell CAMM?Paul A. Clayton2022/12/05 09:49 AMfno-omit-frame-pointer?Gionatan Danti2022/12/03 02:32 AM8086 MOV SS / POP SS interrupt delay... and x86 decoding in generalanonymou52022/11/26 04:38 PMIs 1 more expensive than 0?Andrey2022/11/21 04:23 AMposts disappear ?Michael S2022/11/16 12:41 AMIEEE binary128 support on ARM Macs ?Michael S2022/11/14 03:18 PMx64 successorAvantgarde2022/11/13 04:42 AMWhy is Rosetta 2 fast?Ungo2022/11/10 02:01 PMOne 512-bit vector unit versus 2 256-bit vector units, re Zen 4 AVX-512Jeffrey Bosboom2022/11/04 05:18 PMA16 packaging---2022/10/25 09:45 AMThe Intel 2022-09 ISA ExtensionsAdrian2022/10/20 12:11 AMHow would undocummented, private ISA extensions work in Linux-based systems?Ana Rodriguez2022/10/19 10:12 AMAny die shots of Ryzen 7000 I/O die?hobold2022/10/18 12:52 PMPlaying with fire? Shutting down the Chinese semiconductor industryRay2022/10/14 04:08 PMdownturnanonymou52022/10/12 11:23 AMGPNPU?---2022/10/07 01:40 PMARM new developments 2022dmcq2022/10/07 05:50 AMPat Gelsinger interviewAdrian2022/10/07 04:17 AMSPECworkstation 3Per Hesselgren2022/10/01 05:06 AMNVIDIA Linux driver and Kernel 5.19 & 6.0Philippe2022/09/30 04:14 AMARM announces Armv8.9 and Armv9.4noko2022/09/29 07:02 PMFor Chester: Nvidia’s RTX 4090 Launch---2022/09/28 05:57 PMZen 4 idle power?anonymous22022/09/26 09:32 PMZen4's AVX512 Teardown (from mersenneforum.org)anonymous22022/09/26 07:57 AMA16 Jetstream2 result---2022/09/22 01:46 PMWhy no callee-saved vector registers?Michael S2022/09/20 12:44 PMnew versions of gcc on Debian LinuxMichael S2022/09/19 09:28 AMGH repo to measure core-core latencyanonymous22022/09/18 01:40 PMARM Neoverse V2 - SVE2 is 4x128anonymous22022/09/16 08:04 AMConnectivity issues?Doug S2022/09/15 07:52 PMData integrity of L1 cachesanon22022/09/15 06:04 PMWhat implemention of TSX is present on Sapphire Rapids?Robert Williams2022/09/12 06:58 PMA packaging question---2022/09/11 08:28 PMNo Perf/Clock gains on A16_2022/09/08 03:27 PMforum buganonymou52022/09/01 12:22 AMArm sues over Nuvia/Qualcomm acquisitionWes Felter2022/08/31 02:06 PMNew details on NVidia's Grace server CPUJeff McWilliams2022/08/31 11:20 AMZen 4, AVX-512 support, 2 cycle execution timeanonymous22022/08/29 04:08 PMChips & Cheese analyzes Tachyum’s Revised Prodigy ArchitectureNobod2022/08/27 08:21 AMDo we need branch prediction?Kara2022/08/24 01:07 PMHardware Transactional Memory, the end?rwessel2022/08/20 05:50 PMWhat happened to mill computing? (NT)Kara2022/08/20 01:29 PMZen 4 I/O Die at 6nmanonymous22022/08/18 02:56 PMQualcomm's second server act, after Centriq cancellationBeastian2022/08/18 10:43 AMIntel's abandoned Pentium 5 projecttacobell2022/08/14 12:35 PMZen 4 Infinity Fabric clock reaches 3 GHzWes Felter2022/08/09 12:40 PMAEPIC leakAdrian2022/08/09 11:21 AMInteresting ARM compiler data---2022/08/08 01:54 PMISA (x86/armv8) q: Why isn't "gcc -Os" ~ "gcc -O3" ? (NT)anonymous22022/08/05 09:11 AMTachyum sues Cadence over IP "sabotage"Wes Felter2022/08/03 02:17 PMEmpirical data on ISA design parametersNvaxPlus2022/08/02 07:45 AMWhat kind of FPGA is this?Per Hesselgren2022/07/31 07:48 AMAMD passes Intel in market capanonymous22022/07/29 04:47 PMRIP Optane/XPointWes Felter2022/07/28 06:53 PMCode density comparisonsRayla2022/07/27 12:44 PMCheriBSD running KDEdmcq2022/07/26 02:32 PMIBM 5 bit microcontrollerDuane Sand2022/07/24 10:50 AMHappy 26th anniversary!David Kanter2022/07/23 06:24 PMChina’s SMIC Is Shipping 7nmSomata2022/07/21 01:52 PMMicroinstruction format in older Atom CPUsAdrian2022/07/19 03:57 AMImagination TechnologiesMr. Camel2022/07/15 10:17 AMRetbleedanonymous22022/07/13 02:14 PM[OT] Sturgeon's Observation: reasons for its truth?Paul A. Clayton2022/07/10 04:20 AMIs SVE really Apple's future?---2022/07/09 03:07 PMShape of largest die that fits on reticleMath Nerd2022/07/08 03:57 AMLinear Address Spaces: Unsafe at any speed [article]Kester L2022/06/29 12:49 PMNew ARM Cortex cores launchRayla2022/06/28 07:49 AMEPYC3 refuses to boostMichael S2022/06/28 02:44 AMTSMC's node densities - new article from AngstronomicsBjörn Ragnar Björnsson2022/06/27 11:52 AMNDA balderdash, Arm guessing gameKara2022/06/26 09:55 AMforget transistor size, we're lacking architectsKara2022/06/26 09:17 AMApple memory compression --2022/06/25 12:39 PMOK dumb question timeDoug S2022/06/24 12:31 PMWider vectors vs GPU---2022/06/24 08:43 AMARM refresh MIA?Rayla2022/06/21 09:59 AMP6 High Performance I/O and WebMr. Camel2022/06/21 05:39 AMILP wall vs SIMD vec2022/06/17 11:44 AMM2 benchmarks-2022/06/15 11:27 AMMeasuring latency on Snapdragon devicesJonathan Kang2022/06/14 10:47 AMNew article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/12 06:05 PMZen 4 mobile (Phoenix Point) "chiplet architecture"AngstromAndy2022/06/10 03:46 PMPointer authentication flaw in M1Doug S2022/06/10 10:52 AMBone of contention: AMD resurrects AVX-512 ... sort of ...Björn Ragnar Björnsson2022/06/09 06:00 PMChips, Cheese and Sunny CoveJames2022/06/07 04:57 AMmacOS 13 virtualization framework to support Rosetta 2 inside Linux VMsUngo2022/06/07 12:36 AMPeter Lewis = AIanonymou52022/06/06 04:57 PMApple unveils M2, taking the breakthrough performance and capabilities of M1 even furtherM22022/06/06 11:07 AMGPU Using LPDDR5Someone with gray hair2022/06/03 11:36 AMCrazy CXL NamesPeter Lewis2022/05/30 02:54 PM[Fun] Transform any text into a patent applicationdmcq2022/05/29 01:25 AMIntel Falcon Shores = Xeon CPU + Ponte Vecchio GPU + cache chipJohn R2022/05/27 11:25 AMPerformance of H100 SXM vs H100 PCIeMatt Hughes2022/05/27 02:17 AMZen 4 is really badKara2022/05/26 12:52 AMAddressing in a NoC---2022/05/17 10:02 PMEPYC Instinct ModuleJim Wilson2022/05/12 05:13 PMCache-Coherent Interfaces for High-end GPUsJim Wilson2022/05/12 04:43 PMApple's AVX512---2022/05/11 11:32 PMdisplay "equalization"---2022/05/09 06:30 PMHD vs HP Process---2022/05/05 11:08 AM Side-channel attacks on the data memory-dependent prefetchers in M1ribit2022/05/01 06:00 AMDDR4 & DDR5, new Intel & AMD CPUsBjörn Ragnar Björnsson2022/04/29 06:20 PMWhat's causing 5800X3D to perform much better on simulators than other "applications"?John H2022/04/27 04:20 PMHow maxOS manages M1 CPU coresAndrew Clough2022/04/25 04:11 AMOpenBSD 7.1 is out for Apple M1Brett2022/04/23 10:21 AMFor fans of Minority Report UI's---2022/04/21 11:35 AMApple NVM machine---2022/04/19 03:52 PMvGPUs?---2022/04/15 06:32 PMWhy was enterprise SATA SSDs common for a long time?Yuhong Bao2022/04/15 04:06 AMApple M1 TLB tradeoff anonymous22022/04/14 07:39 AMVLM (on Compaq Alpha) would have been better than AWE...Yuhong Bao2022/04/14 02:20 AMmanufacturing/packaging of the M1 Ultra---2022/04/10 10:26 AMIntel directly copies Zen presentation for Ocean Cove patentphoson2022/04/06 07:03 AMIBM z16 Announcementrwessel2022/04/05 05:31 PMSRAM vs logic scaling with mfg processes - temporary situation, not a real trendHeikki Kultala2022/03/28 10:15 PMCentaur CNS analysisAdrian2022/03/23 01:18 AMPage File SizesZenmont2022/03/22 05:39 PMGPU Microarch DocsKyle Siefring2022/03/22 01:59 PMNvidia H100 Tensor Core GPUHopper2022/03/22 07:48 AMM1 Ultra Chip Interconnect LatencyIan Ameline2022/03/16 12:22 PMRISC-V asm instruction name madnessHeikki Kultala2022/03/09 12:35 AMApple M1 UltraWouter Tinus2022/03/08 11:20 AMIntel to fuse-disable AVX-512 on Alder Lakeanonymous22022/03/04 02:26 PMOptimizing blocksize of data based on memory architecturerocky2022/03/02 11:28 PMFujitsu announce discontinue mainframesBrett2022/02/26 12:59 PMSo the last shall be first...anon22022/02/23 07:25 AM[738 words] Benchmarking interactive systemsPaul A. Clayton2022/02/21 07:51 AMExynos rnda sucks, but didn't everyone know that?Kara2022/02/20 05:57 PMIntel to license x86 coresPaul A. Clayton2022/02/15 12:28 PMAMD Tcase_max data Daniel B2022/02/12 04:26 PMAMD acquiring XilinxKonrad Schwarz2022/02/11 03:21 AMNVIDIA/Arm deal officially offrwessel2022/02/08 05:00 AM Arm has released a prototype of its Morello development board for researchers at Google, Microsoft blaine2022/01/28 03:17 PMIntel to build two fabs in OhioBrett2022/01/23 12:03 AM*guaranteed* IO scheduling---2022/01/14 06:39 PMGoogle TPU architecture evolution paperNet Random2022/01/07 09:26 AMHow good is Intel 7?anon22022/01/04 06:26 PMA Critical Look at SVE2 For Integer Workloads-.-2022/01/02 04:56 PMcache (non)banking---2021/12/26 10:07 PMApple CPU Perf/W. Main FactorKara2021/12/24 07:31 AMNSO Group exploit emulates logic gates!Doug S2021/12/17 11:36 AMElectricity is magnetismBrett2021/12/14 03:01 PMImagination tech back in cpu with risc-vKara2021/12/06 08:48 AMSome info about the Amazon Graviton 3Adrian2021/12/03 05:51 AMCortex a710 merged core SVEKara2021/12/01 10:32 AMCost of rowhammer invulnerability?Chester2021/11/30 07:25 AMSectoring and suchlike in L1 caches---2021/11/29 09:03 PMIntegrated graphics card and discrete graphics card on Linux kernelPhil9955112021/11/26 05:29 PMWhere Walter Jeremiah Sanders III, AMD founder, ended up nowdays?anon2021/11/25 08:42 AMDoes Apple's M1 support BTI (branch target identification)?Gabriele Svelto2021/11/25 01:53 AMSamsung to another build fab in Texas.Brett2021/11/24 02:55 PMForum search more broken than before?Michael S2021/11/18 01:34 PMTop 500, x86 missing from top 4, Intel lagging AMDanonymous22021/11/18 11:17 AMScaling beyond saturationhobold2021/11/10 04:24 AMDetailed investigation of M1 load and store bandwidths from L1 out to DRAM---2021/11/09 01:39 PMThe slow death of technical contentPaul A. Clayton2021/11/08 05:51 AMAlder Lake, not bad, but not as good as expectedAdrian2021/11/04 05:56 AMRun uarch-bench on ADLTravis Downs2021/10/28 11:30 AMM1 Max as a renderer---2021/10/25 08:31 PMIntel IDM 2.0Mr. Camel2021/10/24 03:44 AMYitian 710 anonymous22021/10/20 07:57 PMGB5 Compute results for M1 Max---2021/10/20 12:08 PMApple's "chop" dieDoug S2021/10/19 07:29 AM Introducing M1 Pro and M1 Max: the most powerful chips Apple has ever builtM1 Max2021/10/18 09:59 AMDetails on NVIDIA BlueField-3 Programmable Datapath Accelerator?Paul A. Clayton2021/10/12 11:17 AMCMOS power vs. temperatureDaniel B2021/10/08 08:27 AMApple A15 L1D$Mr. Camel2021/10/07 10:43 AMStrange data point on PC performanceEtienne Lorrain2021/10/06 05:38 AMNios V RISC-V soft coresGabriele Svelto2021/10/05 11:28 PMRemoved thread about linux kernel moduleDavid Kanter2021/09/27 11:26 AMfab capacity or Why are there no GPUs (by Nvidia) to be had?Moritz2021/09/22 05:40 AMArmv8.8-A and Armv9.3-Aanonymou52021/09/16 02:25 PMExtra Apple M1 informationAdrian2021/09/15 11:52 PMz14 and z15 cache latencies?David Kanter2021/09/12 09:40 PMalder lake.inteluser2021/09/10 01:52 AMPOWER10 SAP SD benchmarkanon22021/09/06 02:36 PMApple and RISC-Vvvid2021/09/03 09:47 AMDid IBM Just Preview The Future of Caches?Kester L2021/09/02 07:45 AMAVX512 as co-processorMichael S2021/08/29 02:13 AMIBM's AMX - Apple's wayMichael S2021/08/24 02:43 AMCheck out my tutorial at Hot ChipsDavid Kanter2021/08/22 10:40 AMTesla Project Dojo and InFO_SoWnemo2021/08/20 08:56 AMWas Intel Holding Back?Jon2021/08/19 06:49 AMAlder Lake: 1st Intel/AMD CPU with 6 instruction decodersAdrian2021/08/19 05:21 AMVery-large superscalar execution without the costHugo Décharnes2021/08/18 09:34 AMPost RISC Banked Register InstructionsBrett2021/08/15 11:38 PMSplit TLBsmatthew2021/08/07 09:21 AMIntel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!Kester L2021/07/27 07:29 AMAMX performance on M1 ?Michael S2021/07/27 02:01 AMARM Scalable Matrix Extensiondmcq2021/07/25 04:36 PMHappy 25th anniversary RWTDavid Kanter2021/07/23 05:27 PMShould variable symbols be "signed" with their length in bytes?Etienne Lorrain2021/07/23 01:40 AMDavid – SNRanonymou52021/07/14 02:09 PMinconsistent program state bug in Marvell Octeon TX2?Dummond D. Slow2021/07/12 02:12 PMIs unsafe hell truly good for linux kernel in the future?cqwrteur2021/07/09 08:56 PMIntel discontinued hybrid CPUsGionatan Danti2021/07/07 05:20 AMHigh Bandwidth Memory on Xeon Sapphire RapidsJohn Clarke2021/07/03 06:01 PMIntel to use TSMC 3nm anonymous22021/07/02 11:44 AMInteresting ARM compatibility shim for Windows 11Beastian2021/07/01 01:48 PMAMD EPYC Milan Review Part 2: Testing 8 to 64 Cores in a Production Platformanon2021/06/30 04:36 AMIntel to disable TSX on (more) CPUsanonymous22021/06/28 01:54 PMSiFive to provide its IP to Intel FoundryTriptych2021/06/22 06:24 AMIntel Jasper Lake issue ratesIntelUser20002021/06/16 07:00 PMcomponent availability metadata2021/06/15 12:35 PMIntel interested in acquiring SiFiveGabriele Svelto2021/06/11 12:50 AMGoogle uses AI to design new chipsAndrey2021/06/10 01:20 PMCerebras intros wafer-scale systemanon2021/06/10 05:38 AMAMD 3D VCache at end of year.Brett2021/06/01 12:00 PMWhat's going on with the Arm A510 and Aarch 64?James2021/06/01 04:02 AMM1RACLES (CVE-2021-30747) on Apple M1 siliconGionatan Danti2021/05/29 02:49 AMIntel 10nm SF / Willow Cove now up to 5.3 GHz TVBJohn H2021/05/28 03:33 PM(another?) upcoming self-hosted arm64 optionanonymous22021/05/25 11:40 AMAmpere Altra Max 16MB LLC with 128 coresGanon2021/05/25 12:30 AMOn the RISC-V foundation's inability to ratify new thingsMylin Velodi2021/05/20 02:43 PMAmpere switching to custom coreGionatan Danti2021/05/19 11:56 PMLooks like Apple will be using chipletsDoug S2021/05/18 09:45 AMA Case Against (Most) Context SwitchesLittle Horn2021/05/17 04:03 PMBenefit of push/pop instructionsJörn Engel2021/05/17 11:39 AM"AMD PCI Driver"Rob Thorpe2021/05/16 01:23 AMHow many physical registers are in an Intel CPU (NT)Paul2021/05/13 11:20 PMIce Lake energy efficiency regression?Daniel B2021/05/12 05:52 AMLoongArchRayla2021/05/11 10:00 AMIBM's "2nm" Gate-all-around - will it matter?David Kanter2021/05/10 05:26 PMPost looking at BTB behavior and sizeTravis Downs2021/05/10 01:57 PM4K pages probably used to be too largeYuhong Bao2021/05/01 12:01 PMLeaking Secrets via Intel/AMD Micro-Op CachesAdrian2021/05/01 12:47 AM Older >View archive