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ISA (x86/armv8) q: Why isn't "gcc -Os" ~ "gcc -O3" ? (NT)anonymous22022/08/05 10:11 AM
Tachyum sues Cadence over IP "sabotage"Wes Felter2022/08/03 03:17 PM
Empirical data on ISA design parametersNvaxPlus2022/08/02 08:45 AM
What kind of FPGA is this?Per Hesselgren2022/07/31 08:48 AM
AMD passes Intel in market capanonymous22022/07/29 05:47 PM
RIP Optane/XPointWes Felter2022/07/28 07:53 PM
Code density comparisonsRayla2022/07/27 01:44 PM
CheriBSD running KDEdmcq2022/07/26 03:32 PM
IBM 5 bit microcontrollerDuane Sand2022/07/24 11:50 AM
Happy 26th anniversary!David Kanter2022/07/23 07:24 PM
China’s SMIC Is Shipping 7nmSomata2022/07/21 02:52 PM
Microinstruction format in older Atom CPUsAdrian2022/07/19 04:57 AM
Imagination TechnologiesMr. Camel2022/07/15 11:17 AM
Retbleedanonymous22022/07/13 03:14 PM
[OT] Sturgeon's Observation: reasons for its truth?Paul A. Clayton2022/07/10 05:20 AM
Is SVE really Apple's future?---2022/07/09 04:07 PM
Shape of largest die that fits on reticleMath Nerd2022/07/08 04:57 AM
Linear Address Spaces: Unsafe at any speed [article]Kester L2022/06/29 01:49 PM
New ARM Cortex cores launchRayla2022/06/28 08:49 AM
EPYC3 refuses to boostMichael S2022/06/28 03:44 AM
TSMC's node densities - new article from AngstronomicsBjörn Ragnar Björnsson2022/06/27 12:52 PM
NDA balderdash, Arm guessing gameKara2022/06/26 10:55 AM
forget transistor size, we're lacking architectsKara2022/06/26 10:17 AM
Apple memory compression --2022/06/25 01:39 PM
OK dumb question timeDoug S2022/06/24 01:31 PM
Wider vectors vs GPU---2022/06/24 09:43 AM
ARM refresh MIA?Rayla2022/06/21 10:59 AM
P6 High Performance I/O and WebMr. Camel2022/06/21 06:39 AM
ILP wall vs SIMD vec2022/06/17 12:44 PM
M2 benchmarks-2022/06/15 12:27 PM
Measuring latency on Snapdragon devicesJonathan Kang2022/06/14 11:47 AM
New article: Intel 4 Process Scales Logic with Design, Materials, and EUVDavid Kanter2022/06/12 07:05 PM
Zen 4 mobile (Phoenix Point) "chiplet architecture"AngstromAndy2022/06/10 04:46 PM
Pointer authentication flaw in M1Doug S2022/06/10 11:52 AM
Bone of contention: AMD resurrects AVX-512 ... sort of ...Björn Ragnar Björnsson2022/06/09 07:00 PM
Chips, Cheese and Sunny CoveJames2022/06/07 05:57 AM
macOS 13 virtualization framework to support Rosetta 2 inside Linux VMsUngo2022/06/07 01:36 AM
Peter Lewis = AIanonymou52022/06/06 05:57 PM
Apple unveils M2, taking the breakthrough performance and capabilities of M1 even furtherM22022/06/06 12:07 PM
GPU Using LPDDR5Someone with gray hair2022/06/03 12:36 PM
Crazy CXL NamesPeter Lewis2022/05/30 03:54 PM
[Fun] Transform any text into a patent applicationdmcq2022/05/29 02:25 AM
Intel Falcon Shores = Xeon CPU + Ponte Vecchio GPU + cache chipJohn R2022/05/27 12:25 PM
Performance of H100 SXM vs H100 PCIeMatt Hughes2022/05/27 03:17 AM
Zen 4 is really badKara2022/05/26 01:52 AM
Addressing in a NoC---2022/05/17 11:02 PM
EPYC Instinct ModuleJim Wilson2022/05/12 06:13 PM
Cache-Coherent Interfaces for High-end GPUsJim Wilson2022/05/12 05:43 PM
Apple's AVX512---2022/05/12 12:32 AM
display "equalization"---2022/05/09 07:30 PM
HD vs HP Process---2022/05/05 12:08 PM
Side-channel attacks on the data memory-dependent prefetchers in M1ribit2022/05/01 07:00 AM
DDR4 & DDR5, new Intel & AMD CPUsBjörn Ragnar Björnsson2022/04/29 07:20 PM
What's causing 5800X3D to perform much better on simulators than other "applications"?John H2022/04/27 05:20 PM
How maxOS manages M1 CPU coresAndrew Clough2022/04/25 05:11 AM
OpenBSD 7.1 is out for Apple M1Brett2022/04/23 11:21 AM
For fans of Minority Report UI's---2022/04/21 12:35 PM
Apple NVM machine---2022/04/19 04:52 PM
vGPUs?---2022/04/15 07:32 PM
Why was enterprise SATA SSDs common for a long time?Yuhong Bao2022/04/15 05:06 AM
Apple M1 TLB tradeoff anonymous22022/04/14 08:39 AM
VLM (on Compaq Alpha) would have been better than AWE...Yuhong Bao2022/04/14 03:20 AM
manufacturing/packaging of the M1 Ultra---2022/04/10 11:26 AM
Intel directly copies Zen presentation for Ocean Cove patentphoson2022/04/06 08:03 AM
IBM z16 Announcementrwessel2022/04/05 06:31 PM
SRAM vs logic scaling with mfg processes - temporary situation, not a real trendHeikki Kultala2022/03/28 11:15 PM
Centaur CNS analysisAdrian2022/03/23 02:18 AM
Page File SizesZenmont2022/03/22 06:39 PM
GPU Microarch DocsKyle Siefring2022/03/22 02:59 PM
Nvidia H100 Tensor Core GPUHopper2022/03/22 08:48 AM
M1 Ultra Chip Interconnect LatencyIan Ameline2022/03/16 01:22 PM
RISC-V asm instruction name madnessHeikki Kultala2022/03/09 01:35 AM
Apple M1 UltraWouter Tinus2022/03/08 12:20 PM
Intel to fuse-disable AVX-512 on Alder Lakeanonymous22022/03/04 03:26 PM
Optimizing blocksize of data based on memory architecturerocky2022/03/03 12:28 AM
Fujitsu announce discontinue mainframesBrett2022/02/26 01:59 PM
So the last shall be first...anon22022/02/23 08:25 AM
[738 words] Benchmarking interactive systemsPaul A. Clayton2022/02/21 08:51 AM
Exynos rnda sucks, but didn't everyone know that?Kara2022/02/20 06:57 PM
Intel to license x86 coresPaul A. Clayton2022/02/15 01:28 PM
AMD Tcase_max data Daniel B2022/02/12 05:26 PM
AMD acquiring XilinxKonrad Schwarz2022/02/11 04:21 AM
NVIDIA/Arm deal officially offrwessel2022/02/08 06:00 AM
Arm has released a prototype of its Morello development board for researchers at Google, Microsoft blaine2022/01/28 04:17 PM
Intel to build two fabs in OhioBrett2022/01/23 01:03 AM
*guaranteed* IO scheduling---2022/01/14 07:39 PM
Google TPU architecture evolution paperNet Random2022/01/07 10:26 AM
How good is Intel 7?anon22022/01/04 07:26 PM
A Critical Look at SVE2 For Integer Workloads-.-2022/01/02 05:56 PM
cache (non)banking---2021/12/26 11:07 PM
Apple CPU Perf/W. Main FactorKara2021/12/24 08:31 AM
NSO Group exploit emulates logic gates!Doug S2021/12/17 12:36 PM
Electricity is magnetismBrett2021/12/14 04:01 PM
Imagination tech back in cpu with risc-vKara2021/12/06 09:48 AM
Some info about the Amazon Graviton 3Adrian2021/12/03 06:51 AM
Cortex a710 merged core SVEKara2021/12/01 11:32 AM
Cost of rowhammer invulnerability?Chester2021/11/30 08:25 AM
Sectoring and suchlike in L1 caches---2021/11/29 10:03 PM
Integrated graphics card and discrete graphics card on Linux kernelPhil9955112021/11/26 06:29 PM
Where Walter Jeremiah Sanders III, AMD founder, ended up nowdays?anon2021/11/25 09:42 AM
Does Apple's M1 support BTI (branch target identification)?Gabriele Svelto2021/11/25 02:53 AM
Samsung to another build fab in Texas.Brett2021/11/24 03:55 PM
Forum search more broken than before?Michael S2021/11/18 02:34 PM
Top 500, x86 missing from top 4, Intel lagging AMDanonymous22021/11/18 12:17 PM
Scaling beyond saturationhobold2021/11/10 05:24 AM
Detailed investigation of M1 load and store bandwidths from L1 out to DRAM---2021/11/09 02:39 PM
The slow death of technical contentPaul A. Clayton2021/11/08 06:51 AM
Alder Lake, not bad, but not as good as expectedAdrian2021/11/04 06:56 AM
Run uarch-bench on ADLTravis Downs2021/10/28 12:30 PM
M1 Max as a renderer---2021/10/25 09:31 PM
Intel IDM 2.0Mr. Camel2021/10/24 04:44 AM
Yitian 710 anonymous22021/10/20 08:57 PM
GB5 Compute results for M1 Max---2021/10/20 01:08 PM
Apple's "chop" dieDoug S2021/10/19 08:29 AM
Introducing M1 Pro and M1 Max: the most powerful chips Apple has ever builtM1 Max2021/10/18 10:59 AM
Details on NVIDIA BlueField-3 Programmable Datapath Accelerator?Paul A. Clayton2021/10/12 12:17 PM
CMOS power vs. temperatureDaniel B2021/10/08 09:27 AM
Apple A15 L1D$Mr. Camel2021/10/07 11:43 AM
Strange data point on PC performanceEtienne Lorrain2021/10/06 06:38 AM
Nios V RISC-V soft coresGabriele Svelto2021/10/06 12:28 AM
Removed thread about linux kernel moduleDavid Kanter2021/09/27 12:26 PM
fab capacity or Why are there no GPUs (by Nvidia) to be had?Moritz2021/09/22 06:40 AM
Armv8.8-A and Armv9.3-Aanonymou52021/09/16 03:25 PM
Extra Apple M1 informationAdrian2021/09/16 12:52 AM
z14 and z15 cache latencies?David Kanter2021/09/12 10:40 PM
alder lake.inteluser2021/09/10 02:52 AM
POWER10 SAP SD benchmarkanon22021/09/06 03:36 PM
Apple and RISC-Vvvid2021/09/03 10:47 AM
Did IBM Just Preview The Future of Caches?Kester L2021/09/02 08:45 AM
AVX512 as co-processorMichael S2021/08/29 03:13 AM
IBM's AMX - Apple's wayMichael S2021/08/24 03:43 AM
Check out my tutorial at Hot ChipsDavid Kanter2021/08/22 11:40 AM
Tesla Project Dojo and InFO_SoWnemo2021/08/20 09:56 AM
Was Intel Holding Back?Jon2021/08/19 07:49 AM
Alder Lake: 1st Intel/AMD CPU with 6 instruction decodersAdrian2021/08/19 06:21 AM
Very-large superscalar execution without the costHugo Décharnes2021/08/18 10:34 AM
Post RISC Banked Register InstructionsBrett2021/08/16 12:38 AM
Split TLBsmatthew2021/08/07 10:21 AM
Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!Kester L2021/07/27 08:29 AM
AMX performance on M1 ?Michael S2021/07/27 03:01 AM
ARM Scalable Matrix Extensiondmcq2021/07/25 05:36 PM
Happy 25th anniversary RWTDavid Kanter2021/07/23 06:27 PM
Should variable symbols be "signed" with their length in bytes?Etienne Lorrain2021/07/23 02:40 AM
David – SNRanonymou52021/07/14 03:09 PM
inconsistent program state bug in Marvell Octeon TX2?Dummond D. Slow2021/07/12 03:12 PM
Is unsafe hell truly good for linux kernel in the future?cqwrteur2021/07/09 09:56 PM
Intel discontinued hybrid CPUsGionatan Danti2021/07/07 06:20 AM
High Bandwidth Memory on Xeon Sapphire RapidsJohn Clarke2021/07/03 07:01 PM
Intel to use TSMC 3nm anonymous22021/07/02 12:44 PM
Interesting ARM compatibility shim for Windows 11Beastian2021/07/01 02:48 PM
AMD EPYC Milan Review Part 2: Testing 8 to 64 Cores in a Production Platformanon2021/06/30 05:36 AM
Intel to disable TSX on (more) CPUsanonymous22021/06/28 02:54 PM
SiFive to provide its IP to Intel FoundryTriptych2021/06/22 07:24 AM
Intel Jasper Lake issue ratesIntelUser20002021/06/16 08:00 PM
component availability metadata2021/06/15 01:35 PM
Intel interested in acquiring SiFiveGabriele Svelto2021/06/11 01:50 AM
Google uses AI to design new chipsAndrey2021/06/10 02:20 PM
Cerebras intros wafer-scale systemanon2021/06/10 06:38 AM
AMD 3D VCache at end of year.Brett2021/06/01 01:00 PM
What's going on with the Arm A510 and Aarch 64?James2021/06/01 05:02 AM
M1RACLES (CVE-2021-30747) on Apple M1 siliconGionatan Danti2021/05/29 03:49 AM
Intel 10nm SF / Willow Cove now up to 5.3 GHz TVBJohn H2021/05/28 04:33 PM
(another?) upcoming self-hosted arm64 optionanonymous22021/05/25 12:40 PM
Ampere Altra Max 16MB LLC with 128 coresGanon2021/05/25 01:30 AM
On the RISC-V foundation's inability to ratify new thingsMylin Velodi2021/05/20 03:43 PM
Ampere switching to custom coreGionatan Danti2021/05/20 12:56 AM
Looks like Apple will be using chipletsDoug S2021/05/18 10:45 AM
A Case Against (Most) Context SwitchesLittle Horn2021/05/17 05:03 PM
Benefit of push/pop instructionsJörn Engel2021/05/17 12:39 PM
"AMD PCI Driver"Rob Thorpe2021/05/16 02:23 AM
How many physical registers are in an Intel CPU (NT)Paul2021/05/14 12:20 AM
Ice Lake energy efficiency regression?Daniel B2021/05/12 06:52 AM
LoongArchRayla2021/05/11 11:00 AM
IBM's "2nm" Gate-all-around - will it matter?David Kanter2021/05/10 06:26 PM
Post looking at BTB behavior and sizeTravis Downs2021/05/10 02:57 PM
4K pages probably used to be too largeYuhong Bao2021/05/01 01:01 PM
Leaking Secrets via Intel/AMD Micro-Op CachesAdrian2021/05/01 01:47 AM
Optimal pipelengthPer Hesselgren2021/04/29 09:44 AM
New details on ARM N2 and V1Andrew Clough2021/04/27 07:20 AM
M1 GPU register file sizeryu2021/04/23 04:11 AM
No ARM for NVIDIA?Marcus2021/04/19 06:23 AM
LoongArchLoongShot2021/04/16 03:01 PM
Nvidia Announces ARM HPC CPURayla2021/04/12 09:35 AM
Andre Seznec now at IntelJon Masters2021/04/12 07:53 AM
M1 uarch details Travis Downs2021/04/08 11:58 PM
AMD 5000 processors and PSFPhilippe2021/04/08 10:22 AM
Intel 3rd Gen Xeon Scalable (Ice Lake SP) Reviewanon2021/04/06 10:48 AM
Zen 3 Predictive Store ForwardingRobert Williams2021/04/03 04:33 PM
Please help to test strtod()Michael S2021/04/01 12:02 PM
It's pathetic, but Intel is looking to rename its 10nm as "7nm", 7nm as "5nm". Sadanon2021/03/30 09:40 PM
Armv9 officially announcedJon Masters2021/03/30 11:41 AM
How would you make a VCS for an EDA tool?Paul2021/03/28 08:14 AM
"Purchaser"-designed processors might facilitate asynchronous designPaul A. Clayton2021/03/26 08:22 AM
Intel IFS PDK methodology?Jon Masters2021/03/24 05:22 PM
Intel's IDM 2.0 announcementJon Masters2021/03/23 03:31 PM
Question to Torvalds, how would you make a VCS for an EDA tool?Paul2021/03/20 03:15 PM
What are your ideas for a radically different CPU ISA + physical Arch?Moritz2021/03/20 05:21 AM
Qualcomm Completes Acquisition of NUVIAanonymous22021/03/17 05:25 PM
Intel Ark does not list AVX-512 for Rocket LakeAdrian`2021/03/16 08:39 AM
AnandTech: AMD 3rd Gen EPYC Milan Review: A Peak vs Per Core Performance Balanceanonymous22021/03/15 05:19 PM
Coming attraction: Andy Glew CompArch wikiPaul A. Clayton2021/03/14 07:45 AM
x86 - why unite when you can fragment?anonymou52021/03/12 06:16 PM
MIPS is dead! Long live MIPS!anonymous22021/03/08 12:00 PM
M1 instruction timings and other detailsTravis Downs2021/03/07 10:53 PM
Side Channel Attacks on the CPU On-Chip Ring Interconnect Are Practicalanonymous22021/03/07 10:41 PM
A concrete toy example of the benefits of AVX512Ganon2021/03/06 11:50 PM
Apple M1 Firestorm branch misprediction penaltyDave Liu2021/03/06 06:31 AM
ICL065: move elimination broken in Ice LakeTravis Downs2021/03/06 12:00 AM
AVX-512 and Rocket LakeAnon2021/03/05 06:04 PM
CPU & Memory bit flipsGanon2021/03/03 10:05 AM
AMD Zen4 core in EPYC “Genoa” support AVX-512 instructionsAVX5122021/03/01 03:34 AM
R.I.P. Frys ElectronicsRobert Williams2021/02/24 01:14 PM
Notes on Graviton 2 store behaviorTravis Downs2021/02/24 12:36 AM
Ring vs mesh LLC bandwidthTravis Downs2021/02/22 11:40 PM
New Lex Fridman interview with Jim KellerJohnG2021/02/20 12:25 AM
Crossbar GQTravis Downs2021/02/19 09:05 PM
FPU cut down on PS5 Zen 2 cores?Chester2021/02/14 07:04 PM
Apple GPU reverse engineeringDavid Kanter2021/02/14 11:50 AM
MacOS memory free timingsDavid Kanter2021/02/14 11:42 AM
Anandtech X1 review - unimpressiveAnon2021/02/08 07:37 PM
An interesting approach to memset()Gabriele Svelto2021/02/05 05:30 AM
IDIV r64Per Hesselgren2021/02/04 03:49 AM
Agner Manual Updated for Zen 3Chester2021/02/03 01:33 AM
GB5 on ADLanonymou52021/02/03 12:24 AM
Saturation Curveshobold2021/02/02 05:58 AM
The case for 128-bit ISA:s?Marcus2021/01/26 01:41 PM
did high frequency trading switch?hobold2021/01/26 03:03 AM
open VP/GM positions at Intel's TMGanonymou52021/01/22 10:50 PM
Tremont clarification: 2x3 decodersDavid Kanter2021/01/21 06:56 PM
Core i3 outsourced to TSMCAlex2021/01/20 10:11 AM
Itanium, with a whimperrwessel2021/01/19 05:45 PM
Charlie says: "Large pink bunny suits are hot". You be the judgeanon2021/01/17 04:43 PM
Question about Spectreanon2021/01/14 07:38 AM
Intel throws in the towel?Michael S2021/01/14 02:34 AM
Energy-efficient superconducting microprocessoranon2021/01/13 11:35 PM
Intel CEO Bob Swan to step down in February, VMware CEO Pat Gelsinger to replace himanonymou52021/01/13 07:32 AM
Qualcomm to Acquire NUVIACdiamond2021/01/13 06:32 AM
Hilarious Fake Tom's Hardware ReviewKyleinFL2021/01/11 02:11 PM
8086 microcode disassemblednone2021/01/08 04:06 AM
Dissecting the Apple M1 GPU, part IWes Felter2021/01/07 11:03 AM
Jim Keller joins Tenstorrent as CTO.2021/01/05 09:13 PM
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