Moderated DiscussionsExpand Threads:YesNoView Last:1 hour2 hours4 hours8 hours12 hours1 day2 days3 days5 days7 days14 days30 days60 daysAllHighlight Last:1 hour2 hours4 hours8 hours12 hours1 day2 days3 days5 days7 days14 days30 days60 daysAllStart New ThreadTopicPosted ByDate8086 microcode disassemblednone2021/01/08 04:06 AMDissecting the Apple M1 GPU, part IWes Felter2021/01/07 11:03 AMJim Keller joins Tenstorrent as CTO.2021/01/05 09:13 PMM1 performanceDavid Kanter2021/01/04 09:36 AMUpgraded VMDavid Kanter2021/01/03 12:02 PMUndocumented custom ISA extensions in Apple's M1Gabriele Svelto2021/01/03 10:42 AMAMD patent on programmable instruction unitsme2021/01/02 07:52 AMRyzen 9 5000 series processor Phil9955112020/12/29 06:12 AMWhere is Centaur CNS?Lokatse2020/12/28 08:56 PMWhy Apple never submits SPEC results? (NT)Michael S2020/12/24 02:09 PMA14 die analysisMaynard Handley2020/12/20 08:46 PMAmpere Altra Q80-33 reviewjuanrga2020/12/18 10:39 AMDecimal floating point on x86 and ARM?anon2020/12/18 09:29 AMCan Intel recover... or are they done?anonymou52020/12/18 02:54 AMIn-band ECC support in recent Atom SoCsGabriele Svelto2020/12/15 04:24 PMTwo questions for LinuxSam2020/12/14 02:48 AMNow this was a bit interesting, reconfigurable transistors achieved with black phosphorusRobert Williams2020/12/13 09:01 AMReport: Following US-China semi split, EU charts its own course to semiconductor independenceanon2020/12/10 01:44 AMSeagate jumps on the RISC-V bandwagonGabriele Svelto2020/12/09 01:38 AMHow long till China produces 5nm?dmcq2020/12/05 04:10 AMM1 GPU microbenchmarks (peak FLOPS)K.K2020/12/05 03:31 AMSo much for internal fragmentationMaynard Handley2020/12/01 04:55 PMCocoa API and IOS ?dieselnutjob2020/12/01 04:59 AM80x86 Instruction Alignment Hint?Brendan2020/11/30 11:29 PMMac in the cliudMaynard Handley2020/11/30 11:25 PMApple has now reached higher single-threaded performance within their phone SoCs than what Intel canJan Vlietinck2020/11/30 08:03 AMlaser for connecting CPU to DRAM?Etienne Lorrain2020/11/30 04:24 AMIs there any vendor capable of releasing an M1 competitor on the open market?Paul2020/11/25 02:59 AMApple M1 TSO + RefCounting optimizationsnksingh2020/11/24 07:24 PMARM serveranon2020/11/24 12:55 PMARM Linux laptop for Mr Torvaldsdieselnutjob2020/11/23 09:30 PMApple shareholders delighted by MagSafeanonymou52020/11/22 08:54 PMThe macOS performance deficitGabriele Svelto2020/11/22 04:02 PMInteresting Zen IPC benchmarksAdrian2020/11/21 08:14 AMThe next Apple chipMaynard Handley2020/11/19 09:22 PMDavid Kanter RWT article: "Why Apple Won’t ARM the MacBook"anon2020/11/19 08:17 PMROCm and FPGAsAndrew Clough2020/11/19 09:38 AMARM 78CMaynard Handley2020/11/18 11:12 PMTensorFlow on M1Maynard Handley2020/11/18 02:15 PMApple vs the rest of the industrybystander2020/11/18 02:09 AMThe 2020 Mac Mini Unleashed: Putting Apple Silicon M1 To The TestAppleM12020/11/17 08:46 AM1st round of M1 GPU benchmarksMaynard Handley2020/11/16 01:46 PM3D coresJon Masters2020/11/14 10:24 AMclang - how to target apple M1?Michael S2020/11/14 09:28 AMQuestion to TorvaldsPaul2020/11/14 04:08 AMQinghua Unigroup bankruptcy fearedPaul2020/11/14 03:27 AMRAM on package, like M1, pros and consrpg2020/11/13 08:59 AMXilinx/Samsung SmartSSDsJ2020/11/13 05:46 AMAndrei, thanks for your Zen and Apple articlesMark Roulo2020/11/11 05:19 PMApple Silicon M1 (what to expect based on the A14)juanrga2020/11/11 02:05 AMCXL 2.0 finalizedRobert Williams2020/11/10 09:56 AMZen 3 SOGanon2020/11/07 03:05 PMWhy did Zen start with 4 cores per CCX?John H2020/11/07 10:29 AMMore Zen 3 detailsChester2020/11/05 11:10 AMAmazing podcastJon Masters2020/11/05 09:54 AMDecoder Override event on AMDChester2020/11/03 05:27 PMLeaked internal marketing meeting at Intel :-)Adrian2020/11/03 01:52 PMIntel is bringing HBM to CPUs after allPaul2020/11/03 02:51 AMMemory Performance at SisoftPer Hesselgren2020/11/02 05:54 AMFT: Huawei to start indigenous Chinese 45nm fabrication plant, transitioning to 28nm by end of 2021anon2020/11/01 12:29 PMZen 3 triple FMA unitsAdrian2020/10/30 12:37 PMRocket Lake 14nm back ported from 10nmBrett2020/10/29 08:43 AMAMD - Xilinx merger. Potential technical synergies?Björn Ragnar Björnsson2020/10/27 04:03 PMArm's Custom Datatpath Extensiondmcq2020/10/26 02:27 PMFeature of (data) type for AIMoritz2020/10/23 03:15 AMUnexpected back-to-back L1 performanceAntoine2020/10/15 03:31 PMImagination launches IP for multi-chip GPUsAnon2020/10/15 01:56 AMToday's Apple EventMaynard Handley2020/10/13 12:24 PMAmd is to Xilinx as Intel is to Altera; why now?anon2020/10/08 09:37 PMZen 3Blue2020/10/08 09:58 AMARM server in real worldMaynard Handley2020/10/08 09:52 AMARM Makalu to be +30% over Cortex-A78 in SPECint single-thread (gains slowing down a bit?)Dummond D. Slow2020/10/08 07:15 AMNew Intel Architecture Terms of ServiceAnon2020/10/07 01:02 PMAMD way prediction method (and side channel)Paul A. Clayton2020/10/04 06:05 AMx86 User InterruptsJohn Smith2020/10/03 06:17 AMPlausible A4 numbersMaynard Handley2020/10/02 10:19 PMWindows for ARM getting AMD64 emulationAnon2020/09/30 01:00 PMMemtest86+ 5.01Etienne Lorrain2020/09/28 12:59 AMIntel Elkhart LakeTremont2020/09/23 09:38 AMFill L2 on L2 miss or L1 only?Travis Downs2020/09/23 09:12 AMImagination whitepaper on the six levels of ray tracing accelerationSalvatore De Dominicis2020/09/22 08:48 AMARM annouces new V1 and N2 coresAndrew Clough2020/09/22 06:48 AMPaper recommendationMaynard Handley2020/09/21 12:05 PMJohn Carmack on XR2 / 865Beastian2020/09/19 10:56 AMTiger Lake performance profileanon2020/09/17 07:10 PMIBM open sources A2O out of order coreanon22020/09/16 12:34 AMspeculation *beyond* retirementTravis Downs2020/09/14 07:02 PMBook RecommendationMaynard Handley2020/09/14 06:40 PMNV to Acquire ARM (deal close?)anonymous22020/09/12 12:58 PMHelp a CPU guy understand GPU ALUs (scalar vs vector)Rudolf K.2020/09/05 02:48 AMx64-64 pointer arithmetics between 47 and 48 bits - there is a 47-bit barrier?Heikki Kultala2020/09/01 03:43 AMUseful side effect of our recent autovectorization discussionMichael S2020/08/31 05:22 AMSlack channel, discord, etc. for RWT?David Kanter2020/08/29 03:19 PMA rather premature predictiondmcq2020/08/28 07:04 AMnovel store/load transformations observed in Zen 2Jeff S.2020/08/28 06:05 AMVery little downclocking in client ICLTravis Downs2020/08/19 11:54 AMHot Chips Photonicsdmcq2020/08/19 03:58 AMSrcs of core speedupMaynard Handley2020/08/18 11:04 AMARM and standards for power-saving and other thingsRob Thorpe2020/08/17 08:25 AMHot Chips slack hangout #h-rwt, come visit!David Kanter2020/08/17 07:39 AMThunderX3Rayla2020/08/17 07:17 AMIBM introduces POWER10Crystal S. Diamond2020/08/16 10:20 PMAn insider’s view of Intel’s process woesHnreader2020/08/15 10:11 AMSource of ARM ISA advantage?joema2020/08/15 09:48 AMTigerlake documents?Michael S2020/08/14 01:20 AMIntel graphics quantum leap... again?anny2020/08/13 08:39 AMIntel 10nm "SuperFin"John H2020/08/12 12:57 PMNUVIA PhoenixAdrian2020/08/11 11:00 AMIce Lake mobile: Magnetic Inductor Arrays for FIVRjokerman2020/08/11 08:27 AMAMD big.LITTLE? Jose2020/08/10 04:01 AMSome Intel 10nm+ detailsjokerman2020/08/09 11:58 AMSMT Solving on an iPhone (A12 vs i7-7700k)anonymous22020/08/09 10:43 AMBasicBlockerAdrian2020/08/08 09:37 AMF. Piednoel on Intel's woesBeastian2020/08/05 08:09 PMSequential consistency in hardwarenever_released2020/08/03 08:44 AMThe x86 tax -- ThunderX2/X3juanrga2020/07/31 03:24 AMApple Silicon switchable memory modelTravis Downs2020/07/29 08:59 PMLLC on multi-socketPurple People Eater2020/07/28 02:25 PMmore change at Intelanonymou52020/07/27 04:41 PMlatest Fritzchens Fritz die pics: SKX and KNLanonymou52020/07/26 01:34 AMBranch prediction defaults and hintsTravis Downs2020/07/25 07:41 PMIntel announces 7nm delayDoug S2020/07/23 03:12 PMARM "for sale"anonymous22020/07/23 12:51 PMRWT turns 24David Kanter2020/07/23 10:28 AMIntel Cooper LakeAnon2020/07/22 10:58 PME-Commerce Buyer for PC Components UnexperiencedBuyer2020/07/22 02:18 PMModern coresMaynard Handley2020/07/22 10:03 AMMaybe we get both our wishes in 2020?Maynard Handley2020/07/17 06:09 PMIntel Alder Lake supports AVX-512 despite what others might have misunderstoodAlderLake2020/07/13 09:55 AMSkylake-SP area breakdownDavid Kanter2020/07/12 06:13 PMintel ark portal dead?Michael S2020/07/12 12:22 PMAlder Lake and AVX-512me2020/07/11 07:02 AMIntel Focused Value PredictionFVP2020/07/07 05:29 AMApple confirms dumping AMD GPU support in WWDC 2020 presentationAppleGPU2020/07/07 01:01 AMConcurrency costsTravis Downs2020/07/06 07:26 PMTwo more pieces are filled in...Maynard Handley2020/07/05 12:16 AMSmall 5" bezel-less smartphone project OneDevice.Pierre-Louis Boyer2020/07/01 06:44 AMLoad-Acquire vs Load-AcquirePCMichael S2020/07/01 02:15 AMInterestingMaynard Handley2020/06/29 10:55 AMRosetta 2 benchmarkNiels Jørgen Kruse2020/06/29 09:12 AMWhere does the OS run in a hetero-core? (HPC, IBM, ARM)David Kanter2020/06/28 10:58 AMIf we petition Apple can we get them to open source the upcoming A14 chip's RTL ?anon2020/06/27 08:28 PMARM smartphone share?anonymous22020/06/26 09:08 PMReducing self-modifying code / single-use JIT performance penaltyNyan2020/06/26 09:06 PMIce Lake statusMichael S2020/06/26 08:10 AMIntel Advanced Matrix Extensions (Intel AMX) instruction set in Intel Sapphire RapidsAMX2020/06/26 05:21 AMApple dumped x86 because Skylake sucked?Doug S2020/06/25 10:58 PMidea for iMac Pro in 2021 Michael S2020/06/25 01:15 AMAMD on MacsMaynard Handley2020/06/24 07:36 PMSummary on Arm macsnever_released2020/06/24 11:16 AMAnandtech says Rosetta 2 won't support AVXDoug S2020/06/23 03:45 AMDoes transition to Apple Silicon mean no more discrete AMD GPU?Geert Bosch2020/06/22 08:38 PMWoo Hoo!!!!!!!Maynard Handley2020/06/22 11:26 AMTPUv3 paper at CACMDavid Kanter2020/06/21 10:32 AMouch!Maynard Handley2020/06/20 10:40 AMFine-grained binning of OOOE structuresTravis Downs2020/06/18 05:40 PMJim Keller unexpectedly leaves Intelanonymou52020/06/11 03:32 PMSpecial Register Buffer Data Sampling (Intel CPU exploit)anonymous22020/06/09 10:55 AMAMD Zen with ARM front-endPaul2020/06/09 06:13 AMApple Plans to Announce Move to Its Own Mac Chips at WWDCClaire McDonald2020/06/09 04:47 AMRumor: AMD C7 (ARM Cortext-X1/A78/...)anonymous22020/06/02 11:23 PMUnderstanding Cortex M4F instructions timingMichael S2020/06/01 11:07 AMISCA 2020 Intel paper: Focused Value Predictionanonymou52020/05/30 04:52 PMWhy are split L2 caches unpopular?anon22020/05/30 04:37 PMWhat secrets does the kernel have?Paul A. Clayton2020/05/28 01:47 PMARM L1$ and L2$ replacement algorithimblaine2020/05/27 02:57 PMARMARM cortex A78 and X1 releasedp2020/05/26 03:03 PMkreg (mask) register file shared with MMX/x87Travis Downs2020/05/26 12:17 AMOld school (~1995-2003) frequency scaling vs today within a single node?John H2020/05/23 05:32 AMComing compute style?Moritz2020/05/22 01:20 AMPowerPC takes a risky stepanon2020/05/22 12:04 AMWhat are these white parts?Travis Downs2020/05/21 09:20 AMNew Intel Optimization manualanon2020/05/21 07:54 AMNew article: Transistor count: A Flawed MetricDavid Kanter2020/05/18 07:04 AMTSMC halts new Huawei orders after US tightens restrictionsdmcq2020/05/18 03:46 AMStaggered timer interrupt?Paul A. Clayton2020/05/16 02:42 PM12 ways to fool the masses (HPC)Paul A. Clayton2020/05/16 02:41 PMThe bombshellPaul2020/05/15 12:19 AMNVIDIA Ampere Architecture In-DepthAmpere2020/05/14 07:15 AMSkylake CPU can eliminate some zero-on-zero writesTravis Downs2020/05/13 03:09 PMNew article: Power Delivery in a Modern ProcessorDavid Kanter2020/05/11 07:37 AMgoogle maps on firefoxMichael S2020/05/10 01:49 PM68K equivalent of Pentium Chronicles?John H2020/05/09 04:14 AMI-to-M transitionTravis Downs2020/05/01 04:17 PMIntel removed ECC support from latest i3 CPUsMaxwell2020/04/30 05:27 PMPost-Silicon CPU Adaptationanon2020/04/29 08:59 PMOpenCL 3.0Laurent2020/04/28 08:06 PMHigh res SKL-SP die shotTravis Downs2020/04/27 05:19 PMUnneccessary MUXesMoritz2020/04/27 12:41 PMIt's now a rumor in the mainstreamMaynard Handley2020/04/23 09:02 AMCome see my MLPerf talk at GTCDavid Kanter2020/04/15 08:23 PMConstraints on clock frequencyAndrew Clough2020/04/15 11:08 AMGoogle building its own phone SoCAnon2020/04/14 01:40 PMTiger lake leak, Intel 10nm fixed?Tiger Lake Leaks2020/04/14 09:30 AMIntel V0LTpwn vs. SGXAdrian2020/04/12 03:38 AMDoes Alexa offer genuine automation? How about Google Home?Maynard Handley2020/04/10 07:03 PMIncreasing the number of "in flight" instructions on OoO processorsEtienne2020/04/07 12:50 AMCanyon Bridge Capital seeks to appoint 4 board members to ImgTecBenji Gifford2020/04/04 05:48 PMTachyum Prodigy detailsAdrian2020/04/03 04:17 AMWhy not initialize all variables to zero?Doug S2020/03/26 12:13 PMIntel Rocket Lake-SRocket Lake2020/03/22 09:53 AMA12ZMaynard Handley2020/03/18 10:51 AMAMD has ray tracing in the xboxxbox curious2020/03/18 08:26 AMDo you really need a sense amplifier for MRAM?Paul2020/03/13 01:37 AMLVIanonymou52020/03/10 10:11 AMTRRespassanonymou52020/03/10 10:08 AMAnandtech Graviton2 review with SPECnobody in particular2020/03/10 05:44 AMgcc is a fine compiler but... 2020-03Michael S2020/03/09 03:05 PMA64FX microarchitecture manualnone2020/03/09 10:26 AMAre Intel CPU top guns are still working for them?Michael S2020/03/09 09:47 AMCascade Lake L3 Adaptive Replacement Policyanon2020/03/08 02:24 PMIntel Alder Lake has 8 big cores(Golden Cove?) and 8 small cores(Gracemont?)Alder Lake2020/03/08 12:16 PMRelevant to Nuvia?Maynard Handley2020/03/05 12:22 PMSpeaking of using native OS functionalityMaynard Handley2020/03/03 02:46 PMCost of starting a thread on different microarchitecturesanon2020/03/01 05:03 AMI want to make a proper workstation class laptopPaul2020/02/26 06:22 PMARM based MACsJose2020/02/25 04:56 AMZen2 ISSCC slidesitsmydamnation2020/02/21 03:07 PMHas there ever been a CPU with ...Moritz2020/02/21 08:11 AMARM custom instructionsGabriele Svelto2020/02/18 08:43 AMThe indescribable stupidity of bfloat16Hans de Vries2020/02/18 05:35 AMAMD Family 17h Instruction Latencies spreadsheet ?Michael S2020/02/11 03:05 AMARM announces Cortex M55 and Ethos-U55 Andrew Clough2020/02/10 12:31 PMclang is a fine compiler but...Michael S2020/02/08 12:28 PMLoad-Store architecture vs direct memory ops tradeoffs , and micro-ops - what am I missing?Heikki Kultala2020/02/05 04:26 AMflag merging uops on SkylakeTravis Downs2020/01/26 01:20 PMWhat are ports, really?Travis Downs2020/01/24 01:16 PMLogic in leading foundry process nodesMoritz2020/01/24 11:28 AMCentaur Technologies AMA on Reddit-.-2020/01/22 09:42 PM*Interesting*Maynard Handley2020/01/20 02:50 PMaarch64 online compiler explorersMichael S2020/01/19 08:08 AMAVX-512 downclocking postTravis Downs2020/01/16 09:20 PMLLVM comments on mem*Maynard Handley2020/01/14 01:51 PMSKX IVRTravis Downs2020/01/12 08:28 PMweird movd + ymmTravis Downs2020/01/06 04:48 PMboth rwt forum and site are slow. Is it just me? (NT)Michael S2020/01/05 02:35 PMNuances related to Spinlock implementation and the Linux SchedulerBeastian2020/01/03 12:46 PMOn package stacked memoryPaul2020/01/02 11:00 PMSo the Apple GPU was really a PowerVR after allGabriele Svelto2020/01/02 02:22 PM< NewerOlder >View archive