Moderated DiscussionsExpand Threads:YesNoView Last:1 hour2 hours4 hours8 hours12 hours1 day2 days3 days5 days7 days14 days30 days60 daysAllHighlight Last:1 hour2 hours4 hours8 hours12 hours1 day2 days3 days5 days7 days14 days30 days60 daysAllStart New ThreadTopicPosted ByDateLeaking Secrets via Intel/AMD Micro-Op CachesAdrian2021/05/01 12:47 AMOptimal pipelengthPer Hesselgren2021/04/29 08:44 AMNew details on ARM N2 and V1Andrew Clough2021/04/27 06:20 AMM1 GPU register file sizeryu2021/04/23 03:11 AMNo ARM for NVIDIA?Marcus2021/04/19 05:23 AMLoongArchLoongShot2021/04/16 02:01 PMNvidia Announces ARM HPC CPURayla2021/04/12 08:35 AMAndre Seznec now at IntelJon Masters2021/04/12 06:53 AMM1 uarch details Travis Downs2021/04/08 10:58 PMAMD 5000 processors and PSFPhilippe2021/04/08 09:22 AMIntel 3rd Gen Xeon Scalable (Ice Lake SP) Reviewanon2021/04/06 09:48 AMZen 3 Predictive Store ForwardingRobert Williams2021/04/03 03:33 PMPlease help to test strtod()Michael S2021/04/01 11:02 AMIt's pathetic, but Intel is looking to rename its 10nm as "7nm", 7nm as "5nm". Sadanon2021/03/30 08:40 PMArmv9 officially announcedJon Masters2021/03/30 10:41 AMHow would you make a VCS for an EDA tool?Paul2021/03/28 07:14 AM"Purchaser"-designed processors might facilitate asynchronous designPaul A. Clayton2021/03/26 07:22 AMIntel IFS PDK methodology?Jon Masters2021/03/24 04:22 PMIntel's IDM 2.0 announcementJon Masters2021/03/23 02:31 PMQuestion to Torvalds, how would you make a VCS for an EDA tool?Paul2021/03/20 02:15 PMWhat are your ideas for a radically different CPU ISA + physical Arch?Moritz2021/03/20 04:21 AMQualcomm Completes Acquisition of NUVIAanonymous22021/03/17 04:25 PMIntel Ark does not list AVX-512 for Rocket LakeAdrian`2021/03/16 07:39 AMAnandTech: AMD 3rd Gen EPYC Milan Review: A Peak vs Per Core Performance Balanceanonymous22021/03/15 04:19 PMComing attraction: Andy Glew CompArch wikiPaul A. Clayton2021/03/14 06:45 AMx86 - why unite when you can fragment?anonymou52021/03/12 05:16 PMMIPS is dead! Long live MIPS!anonymous22021/03/08 11:00 AMM1 instruction timings and other detailsTravis Downs2021/03/07 09:53 PMSide Channel Attacks on the CPU On-Chip Ring Interconnect Are Practicalanonymous22021/03/07 09:41 PMA concrete toy example of the benefits of AVX512Ganon2021/03/06 10:50 PMApple M1 Firestorm branch misprediction penaltyDave Liu2021/03/06 05:31 AMICL065: move elimination broken in Ice LakeTravis Downs2021/03/05 11:00 PMAVX-512 and Rocket LakeAnon2021/03/05 05:04 PMCPU & Memory bit flipsGanon2021/03/03 09:05 AMAMD Zen4 core in EPYC “Genoa” support AVX-512 instructionsAVX5122021/03/01 02:34 AMR.I.P. Frys ElectronicsRobert Williams2021/02/24 12:14 PMNotes on Graviton 2 store behaviorTravis Downs2021/02/23 11:36 PMRing vs mesh LLC bandwidthTravis Downs2021/02/22 10:40 PMNew Lex Fridman interview with Jim KellerJohnG2021/02/19 11:25 PMCrossbar GQTravis Downs2021/02/19 08:05 PMFPU cut down on PS5 Zen 2 cores?Chester2021/02/14 06:04 PMApple GPU reverse engineeringDavid Kanter2021/02/14 10:50 AMMacOS memory free timingsDavid Kanter2021/02/14 10:42 AMAnandtech X1 review - unimpressiveAnon2021/02/08 06:37 PMAn interesting approach to memset()Gabriele Svelto2021/02/05 04:30 AMIDIV r64Per Hesselgren2021/02/04 02:49 AMAgner Manual Updated for Zen 3Chester2021/02/03 12:33 AMGB5 on ADLanonymou52021/02/02 11:24 PMSaturation Curveshobold2021/02/02 04:58 AMThe case for 128-bit ISA:s?Marcus2021/01/26 12:41 PMdid high frequency trading switch?hobold2021/01/26 02:03 AMopen VP/GM positions at Intel's TMGanonymou52021/01/22 09:50 PMTremont clarification: 2x3 decodersDavid Kanter2021/01/21 05:56 PMCore i3 outsourced to TSMCAlex2021/01/20 09:11 AMItanium, with a whimperrwessel2021/01/19 04:45 PMCharlie says: "Large pink bunny suits are hot". You be the judgeanon2021/01/17 03:43 PMQuestion about Spectreanon2021/01/14 06:38 AMIntel throws in the towel?Michael S2021/01/14 01:34 AMEnergy-efficient superconducting microprocessoranon2021/01/13 10:35 PMIntel CEO Bob Swan to step down in February, VMware CEO Pat Gelsinger to replace himanonymou52021/01/13 06:32 AMQualcomm to Acquire NUVIACdiamond2021/01/13 05:32 AMHilarious Fake Tom's Hardware ReviewKyleinFL2021/01/11 01:11 PM8086 microcode disassemblednone2021/01/08 03:06 AMDissecting the Apple M1 GPU, part IWes Felter2021/01/07 10:03 AMJim Keller joins Tenstorrent as CTO.2021/01/05 08:13 PMM1 performanceDavid Kanter2021/01/04 08:36 AMUpgraded VMDavid Kanter2021/01/03 11:02 AMUndocumented custom ISA extensions in Apple's M1Gabriele Svelto2021/01/03 09:42 AMAMD patent on programmable instruction unitsme2021/01/02 06:52 AMRyzen 9 5000 series processor Phil9955112020/12/29 05:12 AMWhere is Centaur CNS?Lokatse2020/12/28 07:56 PMWhy Apple never submits SPEC results? (NT)Michael S2020/12/24 01:09 PMA14 die analysisMaynard Handley2020/12/20 07:46 PMAmpere Altra Q80-33 reviewjuanrga2020/12/18 09:39 AMDecimal floating point on x86 and ARM?anon2020/12/18 08:29 AMCan Intel recover... or are they done?anonymou52020/12/18 01:54 AMIn-band ECC support in recent Atom SoCsGabriele Svelto2020/12/15 03:24 PMTwo questions for LinuxSam2020/12/14 01:48 AMNow this was a bit interesting, reconfigurable transistors achieved with black phosphorusRobert Williams2020/12/13 08:01 AMReport: Following US-China semi split, EU charts its own course to semiconductor independenceanon2020/12/10 12:44 AMSeagate jumps on the RISC-V bandwagonGabriele Svelto2020/12/09 12:38 AMHow long till China produces 5nm?dmcq2020/12/05 03:10 AMM1 GPU microbenchmarks (peak FLOPS)K.K2020/12/05 02:31 AMSo much for internal fragmentationMaynard Handley2020/12/01 03:55 PMCocoa API and IOS ?dieselnutjob2020/12/01 03:59 AM80x86 Instruction Alignment Hint?Brendan2020/11/30 10:29 PMMac in the cliudMaynard Handley2020/11/30 10:25 PMApple has now reached higher single-threaded performance within their phone SoCs than what Intel canJan Vlietinck2020/11/30 07:03 AMlaser for connecting CPU to DRAM?Etienne Lorrain2020/11/30 03:24 AMIs there any vendor capable of releasing an M1 competitor on the open market?Paul2020/11/25 01:59 AMApple M1 TSO + RefCounting optimizationsnksingh2020/11/24 06:24 PMARM serveranon2020/11/24 11:55 AMARM Linux laptop for Mr Torvaldsdieselnutjob2020/11/23 08:30 PMApple shareholders delighted by MagSafeanonymou52020/11/22 07:54 PMThe macOS performance deficitGabriele Svelto2020/11/22 03:02 PMInteresting Zen IPC benchmarksAdrian2020/11/21 07:14 AMThe next Apple chipMaynard Handley2020/11/19 08:22 PMDavid Kanter RWT article: "Why Apple Won’t ARM the MacBook"anon2020/11/19 07:17 PMROCm and FPGAsAndrew Clough2020/11/19 08:38 AMARM 78CMaynard Handley2020/11/18 10:12 PMTensorFlow on M1Maynard Handley2020/11/18 01:15 PMApple vs the rest of the industrybystander2020/11/18 01:09 AMThe 2020 Mac Mini Unleashed: Putting Apple Silicon M1 To The TestAppleM12020/11/17 07:46 AM1st round of M1 GPU benchmarksMaynard Handley2020/11/16 12:46 PM3D coresJon Masters2020/11/14 09:24 AMclang - how to target apple M1?Michael S2020/11/14 08:28 AMQuestion to TorvaldsPaul2020/11/14 03:08 AMQinghua Unigroup bankruptcy fearedPaul2020/11/14 02:27 AMRAM on package, like M1, pros and consrpg2020/11/13 07:59 AMXilinx/Samsung SmartSSDsJ2020/11/13 04:46 AMAndrei, thanks for your Zen and Apple articlesMark Roulo2020/11/11 04:19 PMApple Silicon M1 (what to expect based on the A14)juanrga2020/11/11 01:05 AMCXL 2.0 finalizedRobert Williams2020/11/10 08:56 AMZen 3 SOGanon2020/11/07 02:05 PMWhy did Zen start with 4 cores per CCX?John H2020/11/07 09:29 AMMore Zen 3 detailsChester2020/11/05 10:10 AMAmazing podcastJon Masters2020/11/05 08:54 AMDecoder Override event on AMDChester2020/11/03 04:27 PMLeaked internal marketing meeting at Intel :-)Adrian2020/11/03 12:52 PMIntel is bringing HBM to CPUs after allPaul2020/11/03 01:51 AMMemory Performance at SisoftPer Hesselgren2020/11/02 04:54 AMFT: Huawei to start indigenous Chinese 45nm fabrication plant, transitioning to 28nm by end of 2021anon2020/11/01 11:29 AMZen 3 triple FMA unitsAdrian2020/10/30 11:37 AMRocket Lake 14nm back ported from 10nmBrett2020/10/29 07:43 AMAMD - Xilinx merger. Potential technical synergies?Björn Ragnar Björnsson2020/10/27 03:03 PMArm's Custom Datatpath Extensiondmcq2020/10/26 01:27 PMFeature of (data) type for AIMoritz2020/10/23 02:15 AMUnexpected back-to-back L1 performanceAntoine2020/10/15 02:31 PMImagination launches IP for multi-chip GPUsAnon2020/10/15 12:56 AMToday's Apple EventMaynard Handley2020/10/13 11:24 AMAmd is to Xilinx as Intel is to Altera; why now?anon2020/10/08 08:37 PMZen 3Blue2020/10/08 08:58 AMARM server in real worldMaynard Handley2020/10/08 08:52 AMARM Makalu to be +30% over Cortex-A78 in SPECint single-thread (gains slowing down a bit?)Dummond D. Slow2020/10/08 06:15 AMNew Intel Architecture Terms of ServiceAnon2020/10/07 12:02 PMAMD way prediction method (and side channel)Paul A. Clayton2020/10/04 05:05 AMx86 User InterruptsJohn Smith2020/10/03 05:17 AMPlausible A4 numbersMaynard Handley2020/10/02 09:19 PMWindows for ARM getting AMD64 emulationAnon2020/09/30 12:00 PMMemtest86+ 5.01Etienne Lorrain2020/09/27 11:59 PMIntel Elkhart LakeTremont2020/09/23 08:38 AMFill L2 on L2 miss or L1 only?Travis Downs2020/09/23 08:12 AMImagination whitepaper on the six levels of ray tracing accelerationSalvatore De Dominicis2020/09/22 07:48 AMARM annouces new V1 and N2 coresAndrew Clough2020/09/22 05:48 AMPaper recommendationMaynard Handley2020/09/21 11:05 AMJohn Carmack on XR2 / 865Beastian2020/09/19 09:56 AMTiger Lake performance profileanon2020/09/17 06:10 PMIBM open sources A2O out of order coreanon22020/09/15 11:34 PMspeculation *beyond* retirementTravis Downs2020/09/14 06:02 PMBook RecommendationMaynard Handley2020/09/14 05:40 PMNV to Acquire ARM (deal close?)anonymous22020/09/12 11:58 AMHelp a CPU guy understand GPU ALUs (scalar vs vector)Rudolf K.2020/09/05 01:48 AMx64-64 pointer arithmetics between 47 and 48 bits - there is a 47-bit barrier?Heikki Kultala2020/09/01 02:43 AMUseful side effect of our recent autovectorization discussionMichael S2020/08/31 04:22 AMSlack channel, discord, etc. for RWT?David Kanter2020/08/29 02:19 PMA rather premature predictiondmcq2020/08/28 06:04 AMnovel store/load transformations observed in Zen 2Jeff S.2020/08/28 05:05 AMVery little downclocking in client ICLTravis Downs2020/08/19 10:54 AMHot Chips Photonicsdmcq2020/08/19 02:58 AMSrcs of core speedupMaynard Handley2020/08/18 10:04 AMARM and standards for power-saving and other thingsRob Thorpe2020/08/17 07:25 AMHot Chips slack hangout #h-rwt, come visit!David Kanter2020/08/17 06:39 AMThunderX3Rayla2020/08/17 06:17 AMIBM introduces POWER10Crystal S. Diamond2020/08/16 09:20 PMAn insider’s view of Intel’s process woesHnreader2020/08/15 09:11 AMSource of ARM ISA advantage?joema2020/08/15 08:48 AMTigerlake documents?Michael S2020/08/14 12:20 AMIntel graphics quantum leap... again?anny2020/08/13 07:39 AMIntel 10nm "SuperFin"John H2020/08/12 11:57 AMNUVIA PhoenixAdrian2020/08/11 10:00 AMIce Lake mobile: Magnetic Inductor Arrays for FIVRjokerman2020/08/11 07:27 AMAMD big.LITTLE? Jose2020/08/10 03:01 AMSome Intel 10nm+ detailsjokerman2020/08/09 10:58 AMSMT Solving on an iPhone (A12 vs i7-7700k)anonymous22020/08/09 09:43 AMBasicBlockerAdrian2020/08/08 08:37 AMF. Piednoel on Intel's woesBeastian2020/08/05 07:09 PMSequential consistency in hardwarenever_released2020/08/03 07:44 AMThe x86 tax -- ThunderX2/X3juanrga2020/07/31 02:24 AMApple Silicon switchable memory modelTravis Downs2020/07/29 07:59 PMLLC on multi-socketPurple People Eater2020/07/28 01:25 PMmore change at Intelanonymou52020/07/27 03:41 PMlatest Fritzchens Fritz die pics: SKX and KNLanonymou52020/07/26 12:34 AMBranch prediction defaults and hintsTravis Downs2020/07/25 06:41 PMIntel announces 7nm delayDoug S2020/07/23 02:12 PMARM "for sale"anonymous22020/07/23 11:51 AMRWT turns 24David Kanter2020/07/23 09:28 AMIntel Cooper LakeAnon2020/07/22 09:58 PME-Commerce Buyer for PC Components UnexperiencedBuyer2020/07/22 01:18 PMModern coresMaynard Handley2020/07/22 09:03 AMMaybe we get both our wishes in 2020?Maynard Handley2020/07/17 05:09 PMIntel Alder Lake supports AVX-512 despite what others might have misunderstoodAlderLake2020/07/13 08:55 AMSkylake-SP area breakdownDavid Kanter2020/07/12 05:13 PMintel ark portal dead?Michael S2020/07/12 11:22 AMAlder Lake and AVX-512me2020/07/11 06:02 AMIntel Focused Value PredictionFVP2020/07/07 04:29 AMApple confirms dumping AMD GPU support in WWDC 2020 presentationAppleGPU2020/07/07 12:01 AMConcurrency costsTravis Downs2020/07/06 06:26 PMTwo more pieces are filled in...Maynard Handley2020/07/04 11:16 PMSmall 5" bezel-less smartphone project OneDevice.Pierre-Louis Boyer2020/07/01 05:44 AMLoad-Acquire vs Load-AcquirePCMichael S2020/07/01 01:15 AMInterestingMaynard Handley2020/06/29 09:55 AMRosetta 2 benchmarkNiels Jørgen Kruse2020/06/29 08:12 AMWhere does the OS run in a hetero-core? (HPC, IBM, ARM)David Kanter2020/06/28 09:58 AMIf we petition Apple can we get them to open source the upcoming A14 chip's RTL ?anon2020/06/27 07:28 PMARM smartphone share?anonymous22020/06/26 08:08 PMReducing self-modifying code / single-use JIT performance penaltyNyan2020/06/26 08:06 PMIce Lake statusMichael S2020/06/26 07:10 AMIntel Advanced Matrix Extensions (Intel AMX) instruction set in Intel Sapphire RapidsAMX2020/06/26 04:21 AMApple dumped x86 because Skylake sucked?Doug S2020/06/25 09:58 PMidea for iMac Pro in 2021 Michael S2020/06/25 12:15 AMAMD on MacsMaynard Handley2020/06/24 06:36 PMSummary on Arm macsnever_released2020/06/24 10:16 AMAnandtech says Rosetta 2 won't support AVXDoug S2020/06/23 02:45 AMDoes transition to Apple Silicon mean no more discrete AMD GPU?Geert Bosch2020/06/22 07:38 PMWoo Hoo!!!!!!!Maynard Handley2020/06/22 10:26 AMTPUv3 paper at CACMDavid Kanter2020/06/21 09:32 AMouch!Maynard Handley2020/06/20 09:40 AMFine-grained binning of OOOE structuresTravis Downs2020/06/18 04:40 PMJim Keller unexpectedly leaves Intelanonymou52020/06/11 02:32 PMSpecial Register Buffer Data Sampling (Intel CPU exploit)anonymous22020/06/09 09:55 AMAMD Zen with ARM front-endPaul2020/06/09 05:13 AMApple Plans to Announce Move to Its Own Mac Chips at WWDCClaire McDonald2020/06/09 03:47 AMRumor: AMD C7 (ARM Cortext-X1/A78/...)anonymous22020/06/02 10:23 PMUnderstanding Cortex M4F instructions timingMichael S2020/06/01 10:07 AMISCA 2020 Intel paper: Focused Value Predictionanonymou52020/05/30 03:52 PMWhy are split L2 caches unpopular?anon22020/05/30 03:37 PMWhat secrets does the kernel have?Paul A. Clayton2020/05/28 12:47 PMARM L1$ and L2$ replacement algorithimblaine2020/05/27 01:57 PMARMARM cortex A78 and X1 releasedp2020/05/26 02:03 PMkreg (mask) register file shared with MMX/x87Travis Downs2020/05/25 11:17 PMOld school (~1995-2003) frequency scaling vs today within a single node?John H2020/05/23 04:32 AMComing compute style?Moritz2020/05/22 12:20 AMPowerPC takes a risky stepanon2020/05/21 11:04 PMWhat are these white parts?Travis Downs2020/05/21 08:20 AMNew Intel Optimization manualanon2020/05/21 06:54 AMNew article: Transistor count: A Flawed MetricDavid Kanter2020/05/18 06:04 AMTSMC halts new Huawei orders after US tightens restrictionsdmcq2020/05/18 02:46 AMStaggered timer interrupt?Paul A. Clayton2020/05/16 01:42 PM12 ways to fool the masses (HPC)Paul A. Clayton2020/05/16 01:41 PMThe bombshellPaul2020/05/14 11:19 PMNVIDIA Ampere Architecture In-DepthAmpere2020/05/14 06:15 AMSkylake CPU can eliminate some zero-on-zero writesTravis Downs2020/05/13 02:09 PMNew article: Power Delivery in a Modern ProcessorDavid Kanter2020/05/11 06:37 AM< NewerOlder >View archive