Ian Ollmann (iano@apple.com) on 7/7/10 wrote:
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>Konrad Schwarz (no.spam@no.spam) on 7/7/10 wrote:
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>> Well, all my RISC machines work exactly this way, and I'm sure the x86 people
>> would rather not have to deal with AH, AL, AX, EAX and RAX etc.
>
>Dunno if you think that Power still qualifies for RISC,
yes
>they use a common register format for floating point,

This is precisely the point. Sub-registers, such as AL, AH,
significantly complicate register renaming.

there is a whole set of parallel
>ISA for double and single precision ops that round differently in the 64-bit register.

Because single precision is significantly faster than
double precision, at least when the ISA was designed.

>See also AltiVec and SPE with specific ISA for each.

>Likewise, on the integer side, due to the arithmetic miracles of 2's complement,
>special instructions for smaller integer types aren't required for addition, subtraction
>and low-half multiplication. Just ignore the upper bits. In cases where they matter,
>a cheap AND or sign extend are all that are required to make full multiplication and division work.

Speed-wise, less than full-width integer addition obviously
isn't worth it. All you need, and what RISC ISAs provide,
are sub-full-width loads and stores.

This is one of the inherent benefits of a load/store
architecture.

>So, I'm not really sure that your assertion is true, in that what would be required
>to provide full support for native arithmetic in every data type is probably relatively minor.

This would clutter the instruction set for no gain at all,
occupying code space that could be more profitably used for
other things, such as vector instructions.