a reader (a@b.c) on 7/21/10 wrote:
>
>odd things with store buffer replay? like what?
>
>are you sure it's not just L1D too small?

I agree that the L1 is too small too, but no, it's not as
simple as just a small cache.

On the P4, certain instruction scheduling results in
some nasty replays, and if I recall correctly, one of the
worst cases shows up when you have a load that should hit
the store buffer forwarding case, but for one reason or
another ends up not working out correctly.

Now, you can try to google for the exact details, but iirc,
if you have a load that is close to the store that filled
the location (not entirely unusual, happens on the stack
frame due to register spills etc) the P4 insn scheduler can
end up scheduling the load "too close" to the store, and
the load ends up failing and taking a replay trap. Which
basically re-does the instruction, and you lose 10-20
cycles.

I think there were a few other cases of nasty replays too,
and they really end up depending very subtly about just
which cycle the different micro-ops got scheduled in. When
code works well, the P4 runs like a greased bat out of
hell, and then some very non-obvious things can make the
almost identical code take replay traps all the time and
just come to a crawling halt.

As far as I know, Intel never documented the actual rules,
probably because they defy any kind of simple documentation.
And take the above recollection with a pinch of salt, the
details may be wildly different (but it boils down to the
same thing - certain fairly innocuous instruction patterns
could result in lots of pain in the P4 LD/ST unit).

Linus