Vincent Diepeveen (diep@xs4all.nl) on 7/27/10 wrote:
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>a reader (a@b.c) on 7/22/10 wrote:
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>>it's not easy to pin point why p4 perform so badly on real code.
>
>In general the design sucked ass.
>
>You want to do a shift-right instruction?
>
>Boom 7 cycles penalty.
>
>You wanted a CMOV type instruction (how ELSE to replace a branch?)?

You mean that you fail to imagine how to replace an if-then-else with an other type of instruction than CMOV? You can't be serious! The only explanation of why you have written this sentence seems to me that you want to spread disinformation and false statements in order to keep the general public in stupidity, so that you can claim you are more intelligent.

Considering that you can do the reverse (i.e: replace ANY kind of a complex instruction with a mixture of if-then-else statements and simple bit manipulations) ...

>Boom also BIG penalty.
>
>All sorts of worst cases.
>
>Just give me a chip with 512 pentium3's at 1Ghz at a cheap price.

Yes, that is also what I am wondering about. It was possible to built i386 with 275*1000 transitors. The 8-thread Nehalem has 731*1000*1000 transistors. Why not a chip with 100-1000 simpler x86 cores?

>Nearly no communication between the cores at all, or nearly not at all. No synchronisation
>between caches. Just embarrassingly parallel chip. *nearly* embarrassingly parallel.
>
>Each P3 just its own memory space. Then i can run 128 tasks embarrassingly parallel.