slacker (s@lack.er) on 7/20/10 wrote:
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>Matt Sayler (sayler@thewalrus.org) on 7/20/10 wrote:
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>>Does a speculative fetch (jump target) count?
>
>In this case, nope.
>
>He/She ("?") said that pipelining means there must be some speculative execution.
>As demonstrated by the 486, this is not true.

Why 486? That's too advanced, even 8086 does some form of primitive pipelining (according to http://en.wikipedia.org/wiki/Intel_8086), not to mention the later x86 processors.

>Although "?" went to the effort of explaining that OoO execution engines and speculation
>are different things, it looks like "?" has failed to differentiate between pipelining
>and - I am guessing - branch prediction.

The term "branch prediction" seems too constrained for me in this context. To generalize, it is about the assumptions a pipelined CPU makes about the address of the next instruction to be executed. Those assumptions can go wrong in pathological cases. And these assumptions are present there even if the code contains *no* branch instructions at all. Technically, a CPU does not need any branch instructions in order to be a universal Turing machine, it only needs instructions for writing to memory from which the CPU reads the code. A jump instruction is in fact a highly specialized memory write instruction.

It is pure speculation for an x86 CPU to think that "if the address of the current (non-branch) memory write instruction is ADDR, then the address of the next instruction will be ADDR+1". Writes to registers are OK from this point of view, since the CPU never fetches an instruction from there. In CPUs which are able to do data speculation, even writing a register might cause partial pipeline stalls. (I don't know why I am writing this here, because it seems obvious.)

If you think pipelining in a universal-computation CPU has nothing to do with speculation, you are simply wrong. On the other hand, non-speculative pipelining *is* possible, but only if the CPU is able to mathematically prove that a particular piece of code is never violating any assumptions made by the pipelined architecture. But how many existing CPUs are able to do such proofs?

Similarly, L1/L2 caches without any traces of speculative-ness whatsoever are also possible - provided the CPU is able to actually prove that the memory access patterns in a particular piece of code are fully known in advance. But how many existing CPUs are able to do such proofs? (Considering the design of the x86 ISA, I cannot say I blame them for this inability.)

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CPU 1: Not pipelined, executes N instructions per N cycles (IPC=1). This is simply a finite state machine.

CPU 2: Pipelined. Pipeline length is K. Executes (N+(K-1))/N instructions per cycle (IPC=0.999999) - however this is the *best-case* scenario. The worst-case scenario is that IPC goes down and the lower bound for that is N/K instructions per N cycles (IPC=1/K). (Well, I should use some other constant in the latter case, say K' instead of K, because it depends on the architecture of the pipeline, but as an approximation K is acceptable.)