Article: Parallelism at HotPar 2010
By: Rohit (.delete@this..), August 5, 2010 11:19 am
Room: Moderated Discussions
Richard Cownie (tich@pobox.com) on 8/5/10 wrote:
---------------------------
>I don't know many of the details, though I worked with
>a later vector processor. The rough idea seemed to be
>to combine a very fast scalar cpu, together with a
>bunch of vector registers, and vector instructions
>operating on those instructions, with very low overhead
>for the vector operations (so that you could go fast even
>with short vectors) and with "chaining", i.e. several
>dependent vector instructions could run as a pipeline.
>
>Neat stuff for the time, looks quaint now when you can
>buy 1TFLOPS for $250 or so ...
>
>Anyway, it's not much like LRB.
>
From what I read on Wikipedia, it seems awfully like lrb. As for instruction chaining, I think in order issue @>2GHz is an adequate substitute for that.
---------------------------
>I don't know many of the details, though I worked with
>a later vector processor. The rough idea seemed to be
>to combine a very fast scalar cpu, together with a
>bunch of vector registers, and vector instructions
>operating on those instructions, with very low overhead
>for the vector operations (so that you could go fast even
>with short vectors) and with "chaining", i.e. several
>dependent vector instructions could run as a pipeline.
>
>Neat stuff for the time, looks quaint now when you can
>buy 1TFLOPS for $250 or so ...
>
>Anyway, it's not much like LRB.
>
From what I read on Wikipedia, it seems awfully like lrb. As for instruction chaining, I think in order issue @>2GHz is an adequate substitute for that.
