Article: Parallelism at HotPar 2010
By: Mark Roulo (nothanks.delete@this.xxx.com), August 3, 2010 4:13 pm
Room: Moderated Discussions
Aaron Spink (aaronspink@notearthlink.net) on 8/3/10 wrote:
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>Richard Cownie (tich@pobox.com) on 8/3/10 wrote:
>---------------------------
>And if they don't fit in
>>the rather small L1 caches, then you're not going to get
>>a 4x or 6x speedup from using multiple cores, because
>>everything will go through the shared L2 cache. [/quote]
>
>Which Intel processors have shared L2 cache?
>
Some pre-Nehalem Intel chips had large (2MB-ish) shared L2 caches.
-Mark Roulo
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>Richard Cownie (tich@pobox.com) on 8/3/10 wrote:
>---------------------------
>And if they don't fit in
>>the rather small L1 caches, then you're not going to get
>>a 4x or 6x speedup from using multiple cores, because
>>everything will go through the shared L2 cache. [/quote]
>
>Which Intel processors have shared L2 cache?
>
Some pre-Nehalem Intel chips had large (2MB-ish) shared L2 caches.
-Mark Roulo
