Article: Parallelism at HotPar 2010
By: IntelUser2000 (Intel_user2000.delete@this.yahoo.ca), August 7, 2010 2:32 pm
Room: Moderated Discussions
Kevin G (kevin@cubitdesigns.com) on 8/7/10 wrote:
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>
>The odd thing is that the Pentium 4 had a lower L1 cache latency and it was designed
>for far higher clocks. Though in fairness the L1 cache sizes on the Pentium 4 were smaller.
>
>My personal suspecision for the increase in L1 latencies on Nehalem is due to the
>addition of Hyperthreading and the additional logic necessary for sharing the caches
>between two threads. Also did Nehalem goes from a 6 transistor SRAM to an 8 transistor SRAM design for the L1 cache?
This topic came months ago on RWT. Nehalem moved to all static circuitry, which lowers power usage but slows speeds down. That's likely what attributes to increased L1D cache latencies
---------------------------
>
>The odd thing is that the Pentium 4 had a lower L1 cache latency and it was designed
>for far higher clocks. Though in fairness the L1 cache sizes on the Pentium 4 were smaller.
>
>My personal suspecision for the increase in L1 latencies on Nehalem is due to the
>addition of Hyperthreading and the additional logic necessary for sharing the caches
>between two threads. Also did Nehalem goes from a 6 transistor SRAM to an 8 transistor SRAM design for the L1 cache?
This topic came months ago on RWT. Nehalem moved to all static circuitry, which lowers power usage but slows speeds down. That's likely what attributes to increased L1D cache latencies
