Nicolas Capens (nicolas.capens@gmail.com) on 3/9/11 wrote:
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>To reduce the actual storage needs, the GPU has to become capable of advancing
>its program counter more quickly. It needs CPU technology for that, like the use
>of superscalar execution in NVIDIA's latest chips.

Both NVidia and ATI/AMD have introduced new dual chip high end cards in the $700 segment.
Both are made at 40nm on a TSMC process, so we can compare the tradeoffs and see what the future may look like:
http://www.xbitlabs.com/articles/video/display/geforce-gtx-590.html
http://www.xbitlabs.com/articles/video/display/geforce-gtx-590_11.html

ATI has 3000 simple pipelines at 880 MHz.
NVidia has 1000 out-of-order pipes with part of the chip at twice the clocks.
RESULT: A Draw. (Pun intended.)

Die size ATI 389 mm2, NVidia 520 mm2, so the ATI chip is 75% of the size of NVidia.
This means really bad things for NVidia yields and costs and competitiveness.

ATI is getting ~100% scaling with more pipes, ATI has its software act going warp speed.
Previous software releases showed poor scaling, I was worried they were running out of gas and NVidia would catch up.
(I have a financial interest in AMD, and a desire for Moores law to continue...)

Having three times more simple pipes, seems better, over bigger OoO pipes.

SLI wins, due to power draw, if they had benchmarked the GTX 580 SLI it would have won easily due to the greater bandwidth, but you need a special power supply to power two of them.

There is a HUGE anomaly in that the 50% wider memory bus on the NVidia chips has the same bandwidth as the ATI chips. (384 bits vs 256 bits)
ATI RAM clocked at 5000MHz vs NVidia 3414MHz, 46% faster.

This screams bus thermal limits getting hit.
I bet the interface and DRAM thermals just do not matter, its all the on chip bandwidth thermals that matter...?


>>>>There is a Stanford talk on the limits of power,

>>Stanford University Online has a truly awesome related iTunes talk by Bill Dally:
>> http://itunes.apple.com/itunes-u/programming-massively-parallel/id384233322
>>Watch Track 13, the course "Programming Massively Parallel Processors with CUDA (CS193G)".

You were a heavy poster here, then I posted this link a month ago and you fell off the net... ;)

I am actually a fan of scatter/gather, which you were promoting.
But the simpler form of short offset off a base, useful for decoding OpenGL display lists and similar compressed data.
This can be implemented cheaply, with simple generally sequential cache lines reads until the full request is supplied.
The full four address form requires four address computations and four reads that you have to cross check for cache line duplicates to optimize.
Of course this full form is what you need for texel sampling, which is what you want?

Larrabee tried a full 16 way scatter/gather, I thought they were crazy. ;)
Die size and thermals killed Larrabee twice over?
Intel did impress me by actually designing and manufacturing such a chip.

NVidia and ATI have dedicated texel sample units, this would appear to be the best solution?
The texel unit is close to its data, does 16 samples from its cache, and passes the one result far away to the processor.
If the processor does texel reads then you blow your data cache on texels, and blow the pipeline die size on the scatter/gather unit.
Bigger pipeline is slower and hotter.

Chopping the task up to localize data and computation gives you a massive thermal advantage.

Larrabee hedged its bets by including scatter/gather AND dedicated texel units.
If Larrabee 3 ever sees the light of day we may see some design changes here.

>Cheers,
>
>Nicolas

I put a lot of thought into this post, the problem with that is that I may not get many replies.
Trolls get more feedback. ;)