Michael S (already5chosen@yahoo.com) on 1/23/11 wrote:
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>Taking into account that, according to Optimization reference manual, on 4-core
>models LLC load latency varies by 6 clocks, it does look like 1 clock in each direction.

I guess it is physically possible, but I think that is really fast.
The signal must go up and down a few times to get amplified/driven and make the distance in the same time a single pipeline-stage is completed.
Either that is really fast or the logic clocking is really slow and utterly power/heat limited.