By: ajensen (.delete@this..), November 18, 2010 1:24 am
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 11/17/10 wrote:
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>someone (someone@somewhere.com) on 11/17/10 wrote:
>---------------------------
>>David Kanter (dkanter@realworldtech.com) on 11/17/10 wrote:
>>---------------------------
>>>Of course, Intel might also leave that up to the software...which
>>>would be stupid, but also more philosophically consistent with EPIC.
>>>
>>>David
>>
>>Hmmmm.
>>
>>Montecito didn't leave management of its extremely coarse
>>grained multi-threading up to software so why would Intel
>>attempt that with Poulson's very likely much finer grained
>>multi-threading?
>
>I hope they wouldn't. In fact, I hope that everyone at Intel has gotten on-board
>the train of 'dynamic everything' (except your logic, static CMOS is fine!). Dynamic
>thread management makes a lot of sense.
>
>DK
If they are going to have any fighting chance to keep up on heavily threaded low ILP workloads then the 12 issue pipeline must be able to issue instructions form more than one thread one each and every cycle. That much is obvious even to a hardcore EPIC believer... So is Intel going to disregard that performance class for IPF? Like databases.. I think you have your answer. I certainly wouldn't bet against this.
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>someone (someone@somewhere.com) on 11/17/10 wrote:
>---------------------------
>>David Kanter (dkanter@realworldtech.com) on 11/17/10 wrote:
>>---------------------------
>>>Of course, Intel might also leave that up to the software...which
>>>would be stupid, but also more philosophically consistent with EPIC.
>>>
>>>David
>>
>>Hmmmm.
>>
>>Montecito didn't leave management of its extremely coarse
>>grained multi-threading up to software so why would Intel
>>attempt that with Poulson's very likely much finer grained
>>multi-threading?
>
>I hope they wouldn't. In fact, I hope that everyone at Intel has gotten on-board
>the train of 'dynamic everything' (except your logic, static CMOS is fine!). Dynamic
>thread management makes a lot of sense.
>
>DK
If they are going to have any fighting chance to keep up on heavily threaded low ILP workloads then the 12 issue pipeline must be able to issue instructions form more than one thread one each and every cycle. That much is obvious even to a hardcore EPIC believer... So is Intel going to disregard that performance class for IPF? Like databases.. I think you have your answer. I certainly wouldn't bet against this.