By: Martin Høyer Kristiansen (test.delete@this.example.com), November 18, 2010 12:35 am
Room: Moderated Discussions
someone (someone@somewhere.com) on 11/17/10 wrote:
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>The OOOE logic in the Pentium M consumes about 26%
>of device power and twice as much power it uses actually
>doing computation (i.e. integer and FP data paths). Going
>wider issue and/or larger window burns disproportionally
>more of the power budget.
...And width of the registers. Intel switched back to read-after-schedule (used in P4) for Sandy Bridge because supporting fat result buses would burn much more power.
You can compare the 26% power to the power spent in the result forwarding network in IPF and L1 cache accesses. Without the fantastic D$, IPF performance would be a lot lower. For both architectures, power well spent, IMO.
Cheers
Martin
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>The OOOE logic in the Pentium M consumes about 26%
>of device power and twice as much power it uses actually
>doing computation (i.e. integer and FP data paths). Going
>wider issue and/or larger window burns disproportionally
>more of the power budget.
...And width of the registers. Intel switched back to read-after-schedule (used in P4) for Sandy Bridge because supporting fat result buses would burn much more power.
You can compare the 26% power to the power spent in the result forwarding network in IPF and L1 cache accesses. Without the fantastic D$, IPF performance would be a lot lower. For both architectures, power well spent, IMO.
Cheers
Martin
