By: someone (someone.delete@this.somewhere.com), November 18, 2010 8:30 pm
Room: Moderated Discussions
Groo (charlie@semiaccurate.com) on 11/18/10 wrote:
---------------------------
>someone (someone@somewhere.com) on 11/17/10 wrote:
>---------------------------
>>It burns a lot of power using hundreds of thousands of
>>logic transistors re-discovering something about a scrap
>>of code every single loop iteration or subroutine call for
>>every execution of all copies of program that one compiler
>>need only to discern once. Everything can't be discovered
>>at compile time but it is stupid to ignore that which can
>>be and then passed on using a suitable equipped ISA.
>
>How much power does a cache miss or a stall consume?
>
>-Charlie
I guess you are ignorant of the fact that IA64 includes
means for the compiler to associate hints about the
spacial and temporal locality of the data associated
with each load and store instruction as well as specify
the degree of ordering strictness required between sets
of memory transfers. These features, AFAIK unique to
IA64, allow conflict and capacity misses to be reduced
as well as avoiding stalls from hardware enforcement
of unnecessary memory ordering.
It is funny how negative opinion of IA64 is so highly
correlated with degree of sheer ignorance about it. ;^)
---------------------------
>someone (someone@somewhere.com) on 11/17/10 wrote:
>---------------------------
>>It burns a lot of power using hundreds of thousands of
>>logic transistors re-discovering something about a scrap
>>of code every single loop iteration or subroutine call for
>>every execution of all copies of program that one compiler
>>need only to discern once. Everything can't be discovered
>>at compile time but it is stupid to ignore that which can
>>be and then passed on using a suitable equipped ISA.
>
>How much power does a cache miss or a stall consume?
>
>-Charlie
I guess you are ignorant of the fact that IA64 includes
means for the compiler to associate hints about the
spacial and temporal locality of the data associated
with each load and store instruction as well as specify
the degree of ordering strictness required between sets
of memory transfers. These features, AFAIK unique to
IA64, allow conflict and capacity misses to be reduced
as well as avoiding stalls from hardware enforcement
of unnecessary memory ordering.
It is funny how negative opinion of IA64 is so highly
correlated with degree of sheer ignorance about it. ;^)