ISSCC Poulson Preview Online - OoO not unlikely?

Article: New Itanium Microarchitecture at ISSCC 2011
By: someone (someone.delete@this.somewhere.com), November 21, 2010 10:24 am
Room: Moderated Discussions
Groo (charlie@semiaccurate.com) on 11/20/10 wrote:
---------------------------
>>>How much power does a cache miss or a stall consume?
>
>>I guess you are ignorant of the fact that IA64 includes
>>means for the compiler to associate hints about the
>>spacial and temporal locality of the data associated
>>with each load and store instruction as well as specify
>>the degree of ordering strictness required between sets
>>of memory transfers. These features, AFAIK unique to
>>IA64, allow conflict and capacity misses to be reduced
>>as well as avoiding stalls from hardware enforcement
>>of unnecessary memory ordering.
>>
>I didn't ask that question, I asked about how much power it consumes when it does
>miss. By your rather desperate dodge and childish attacks, I can only infer that
>it is quite a painful number for you to talk about.

I did answer your question in the manner most germane
to this sub-thread but obviously you are too ignorant to
see that. Your subsequent blustery reply only reinforces
the fact for all to see.


>
>>It is funny how negative opinion of IA64 is so highly
>>correlated with degree of sheer ignorance about it. ;^)
>
>It is rather ironic that you change the topic to something I didn't bring up, then
>accuse me of ignorance about it. What are you trying to hide?
>
>Oh yes, can you answer the original question?
>
>-Charlie

Ok, I'll answer your ill posed question literally but you
probably won't like the answer any better.

The energy to process a cache miss has two components,
energy consumed in the cache and memory system and
the energy consumed in the CPU as a result of the miss.
The former depends entirely on the nature and design of
cache and memory system and is not affected by the nature
of the CPU. The energy consumed within the CPU depends
on whether the CPU has aggressive dynamic scheduling
such that a cache miss will always or sometimes generate
a replay trap (which uses energy to effectively back up
the pipeline and re-execute a bunch of instruction). IPF
proccessors to date have exact stall pipelines and do
not generate replay traps thus do not consume extra
energy within the CPU when a cache miss occurs.

The story is similar for stalls. A stall itself does not use
any energy on its own unless the CPU suffers a replay
trap in the course of handling it. IPF processors do not
use replay traps.

Of course energy per individual stall or cache miss
becomes relevant to processor power when combined
with occurrence frequency. As I mentioned before IA64
includes novel features that can be used to reduce the
number of misses and stalls that occur in the course of
executing a given program.

Less frequent occurrence times less energy for each
occurence equals a double win.
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                    ISSCC Poulson Preview Online - OoO not unlikely?someone2010/11/19 11:04 AM
                      ISSCC Poulson Preview Online - OoO not unlikely?Linus Torvalds2010/11/19 11:24 AM
                        ISSCC Poulson Preview Online - OoO not unlikely?someone2010/11/19 12:05 PM
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                            ISSCC Poulson Preview Online - OoO not unlikely?someone2010/11/20 11:02 AM
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