someone (someone@somewhere.com) on 11/21/10 wrote:
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>The leakage power occurs whether the CPU is stalled
>or whether it is not stalled. Therefore it cannot be
>atributed to the stall.

You have a certain amount of work to do. If an OoO gets
the work done in fewer cycles (and then drops into some
lower-power state, which may involve powering down
big chunks of circuitry), then it's going to use less
energy. Conversely, an in-order processor tends to
have a lot of circuitry powered up but not doing anything
useful for the duration of a stall; and tends to end up
needing more cycles to get the work done.

Stalls cost time *and* energy.

>leakage energy per stall. I would counter that the
>extra complexity of OOOE means that there are a lot
>more logic transistors around to leak and so leakage
>power is always higher - whether stalled or not.. :-P

That's a reasonable argument for why Atom might be
power-efficient compared to other x86's (though annoyingly
slow). However, when you try to build a performance-
competitive in-order cpu, you need to go wider-issue
to make up for the fact that you'll often be stalled;
and then the wide-issue gizmology seems to be at least
as big and power-hungry as the OoO gizmology.

Anyhow, they've worked on Itanium for 15+ years and it
has never looked good on performance/watt. And has only
very rarely looked competitive on absolute performance.
So any energy-efficiency benefits of the IPF architecture
would seem to be very very hypothetical.