OOOE and energy efficiency

Article: New Itanium Microarchitecture at ISSCC 2011
By: Chuck (no.delete@this.thanks.com), November 23, 2010 10:04 pm
Room: Moderated Discussions
someone (someone@somewhere.com) on 11/23/10 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 11/23/10 wrote:
>---------------------------
>>
>>I don't believe that OOOE is inherently less power efficient than InO. OOOE lets
>>you overlap more cache misses, which can reduce the amount of time the process is stalled.
>>
>>DK
>
>You are talking about one narrow aspect of architectural
>performance figure of merit, not the full performance vs
>design cost metric or computational power efficiency.
>
>The OOOE vs IOE issue is highly workload dependent. For
>a given issue width and frequency the performance gain
>from OOOE vs in-order is as high as 30-50% for branchy
>scalar code with highly unstructured memory accesses to
>less than 5% for code dominated by predictable control
>flow and memory accesses. That is for implementations
>of non-EPIC ISAs at the same issue width and frequency.
>
>Published research into the benefit of OOOE for EPIC ISAs
>is limited and tends to focus on novel simplified dynamic
>scheduling schemes that aren't full classic OOOE.
>
>Of course OOOE is not free. It adds complexity and power
>consumption (dynamic and static). The power/area cost is
>20 to 40% depending on the issue width and degree of
>OOOE aggressiveness (windows size, speculativity etc).
>Given a fixed amount of resources (silicon area, Watts),
>an in-order implementation can devote more transistors
>and Watts to other CPU functionality, more cache and/or
>higher clock frequency.
>
>Is OOOE worth the cost for general purpose MPUs (i.e.
>intended for a wide range of applications)? The answer
>is yes for most high performance implementations of
>CISC and RISC ISAs although the appearance of modern
>in-order processors like Atom and Power6 suggests the
>question isn't nearly as settled as some like to claim.
>
>What about OOOE for implementations of EPIC ISAs? A
>comparison of McKinley vs EV6 vs Power4 suggests that
>what EPIC brings to the table combined with extra CPU
>resources not going OOOE buys makes the question a
>lot more debatable than with non-EPIC ISAs. My guess
>is Fort Collins looked carefully at OOOE but stayed with
>an in-order design for Poulson to maximize performance
>within its die size and power budget.


We've been through this discussion before Paul. Suffice it to say, you're like the wounded and tied animal that keeps jerking the chain. Same arguments, but expecting different results.

For circa 2000 era MPUs, ia64 processors like McKinley may well have been more "efficient" and less logic intensive than their OoO x86 contemporaries. But you often like to present your argument for the efficiencies of InO vs. OoO processors unqualified, and applying for processors across a range of ISAs, which has been demonstrated to be patently false, misleading, and even intellectually dishonest. For a contemporary of InO McKinley like the OoO EV6 core had 6 million logic transistors (sans cache), to McKinley's 12 million (sans cache & x86 box).

It is more appropriate to compare a single conceptual core instance of a single ISA and evaluate its InO vs. OoO design potential with equivalent fetch, issue width, and execution resources. It is rare the stars align to allow for such a comparison, though the recent ARM A8 vs. A9 cores come close to this ideal. ARM's statements regarding the performance advantages of A9 vs. A8 can be empirically evaluated, in light of the relative complexity of these cores.

Any other statements by you regarding InO ia64 vs. OoO EveryThingElse performance, power, and complexity is meaningless, and should be treated as such.

For the ULSI era 2010 chips of today with large numbers of integrated components and blocks alongside the MPU cores, any core logic transistor advantage InO ia64 had over OoO x86 cores is lost in the noise, due to the relentless drive of integration resulting from Moore's Law. Similarly any core logic transistor advantages OoO RISC had over InO ia64 is also minimized to ULSI.
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