By: lubemark (lubemark.delete@this.davide.it), November 22, 2010 7:02 am
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 11/17/10 wrote:
---------------------------
>First of all, I'd like to give a big thank you to the poster who noticed the ISSCC
>advance program. The paper title regarding Poulson was a great find and well in advance of any one else picking it up.
>
>I wrote a short piece that contains my thoughts and speculation on the upcoming
>Poulson microarchitecture. This is relatively well educated speculation, but speculation
>
nonetheless, and it will be interesting to see the presentation and paper in February.
>
>In the mean time, here's the article for everyone to enjoy:
>http://www.realworldtech.com/page.cfm?ArticleID=RWT111710021604
>
>As always, comments and questions are welcome.
>
>
>David
now the abstract it's on line :
http://isscc.org/doc/2011/isscc2011.advanceprogrambooklet_abstracts.pdf
4.8 a 32nm 3.1 Billion Transistor 12-wide-issue itanium® processor
4:45 pM
for Mission-critical Servers
R. J. Riedlinger1, R. Bhatia1, L. Biro2, B. Bowhill2, E. Fetzer1, P. Gronowski2, T. Grutkowski1
1
Intel, Fort Collins, CO
2
Intel, Hudson, MA
An Itanium® processor implemented in 32nm CMOS with 9 layers of Cu contains 3.1 billion transistors.
The die measures 18.2×29.9mm2. The processor has 8 multi-threaded cores, a ring-based system
interface and combined cache on the die is 50MB. High speed links allow for peak processor-to-
processor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s
first thougths:
1)total cache is 50MB so 6MB L3 is likely
2)ring-based system interface (reminds me original tukwila aka Tanglewood)
3) 8 cores (no surprise here) multi(treaded) means more than two (more likely four)
4) four engineers are from Fort Collins and three from Hudson
now could be nice if David, Paul or anyone else would grab something from the designers before february...
---------------------------
>First of all, I'd like to give a big thank you to the poster who noticed the ISSCC
>advance program. The paper title regarding Poulson was a great find and well in advance of any one else picking it up.
>
>I wrote a short piece that contains my thoughts and speculation on the upcoming
>Poulson microarchitecture. This is relatively well educated speculation, but speculation
>
nonetheless, and it will be interesting to see the presentation and paper in February.
>
>In the mean time, here's the article for everyone to enjoy:
>http://www.realworldtech.com/page.cfm?ArticleID=RWT111710021604
>
>As always, comments and questions are welcome.
>
>
>David
now the abstract it's on line :
http://isscc.org/doc/2011/isscc2011.advanceprogrambooklet_abstracts.pdf
4.8 a 32nm 3.1 Billion Transistor 12-wide-issue itanium® processor
4:45 pM
for Mission-critical Servers
R. J. Riedlinger1, R. Bhatia1, L. Biro2, B. Bowhill2, E. Fetzer1, P. Gronowski2, T. Grutkowski1
1
Intel, Fort Collins, CO
2
Intel, Hudson, MA
An Itanium® processor implemented in 32nm CMOS with 9 layers of Cu contains 3.1 billion transistors.
The die measures 18.2×29.9mm2. The processor has 8 multi-threaded cores, a ring-based system
interface and combined cache on the die is 50MB. High speed links allow for peak processor-to-
processor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s
first thougths:
1)total cache is 50MB so 6MB L3 is likely
2)ring-based system interface (reminds me original tukwila aka Tanglewood)
3) 8 cores (no surprise here) multi(treaded) means more than two (more likely four)
4) four engineers are from Fort Collins and three from Hudson
now could be nice if David, Paul or anyone else would grab something from the designers before february...
