By: David Kanter (dkanter.delete@this.realworldtech.com), November 22, 2010 11:08 am
Room: Moderated Discussions
IntelUser2000 (Intel_user2000@yahoo.ca) on 11/22/10 wrote:
---------------------------
>lubemark (lubemark@davide.it) on 11/22/10 wrote:
>---------------------------
>>now the abstract it's on line :
>>
>>http://isscc.org/doc/2011/isscc2011.advanceprogrambooklet_abstracts.pdf
>>>
>>
>>4.8 a 32nm 3.1 Billion Transistor 12-wide-issue itanium® processor
>>4:45 pM
>>for Mission-critical Servers
>>R. J. Riedlinger1, R. Bhatia1, L. Biro2, B. Bowhill2, E. Fetzer1, P. Gronowski2, T. Grutkowski1
>>1
>>Intel, Fort Collins, CO
>>2
>>Intel, Hudson, MA
>>
>>
>>An Itanium® processor implemented in 32nm CMOS with 9 layers of Cu contains 3.1 billion transistors.
>>The die measures 18.2×29.9mm2. The processor has 8 multi-threaded cores, a ring-based system
>>interface and combined cache on the die is 50MB. High speed links allow for peak processor-to-
>>processor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s
>>
>>first thougths:
>>
>>1)total cache is 50MB so 6MB L3 is likely
>>2)ring-based system interface (reminds me original tukwila aka Tanglewood)
>>3) 8 cores (no surprise here) multi(treaded) means more than two (more likely four)
>>4) four engineers are from Fort Collins and three from Hudson
>>
>>now could be nice if David, Paul or anyone else would grab something from the designers before february...
>>
>
>The only problem with that estimate is that would mean the L2 cache would go from
>independent I and D on Montecito/Montvale/Tukwila back to shared ID with 256KB
>capacity. That's a significant reduction from 1MB+256KB on Montecito/Montvale and 512KB+256KB on Tukwila.
Yeah, I'd say it's a lot more likely that the L3 cache is 4-5MB per core.
As was pointed out, you need your directory cache (2-4MB), your L2D caches (2-4MB), your L2I caches (4-8MB). So I'd guess that each core has 6MB of SRAM total...with the directory cache using up the rest. That leaves around 4-4.5MB of L3 cache, presuming that they use 1MB L2I + 256KB L2D.
David
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>lubemark (lubemark@davide.it) on 11/22/10 wrote:
>---------------------------
>>now the abstract it's on line :
>>
>>http://isscc.org/doc/2011/isscc2011.advanceprogrambooklet_abstracts.pdf
>>>
>>
>>4.8 a 32nm 3.1 Billion Transistor 12-wide-issue itanium® processor
>>4:45 pM
>>for Mission-critical Servers
>>R. J. Riedlinger1, R. Bhatia1, L. Biro2, B. Bowhill2, E. Fetzer1, P. Gronowski2, T. Grutkowski1
>>1
>>Intel, Fort Collins, CO
>>2
>>Intel, Hudson, MA
>>
>>
>>An Itanium® processor implemented in 32nm CMOS with 9 layers of Cu contains 3.1 billion transistors.
>>The die measures 18.2×29.9mm2. The processor has 8 multi-threaded cores, a ring-based system
>>interface and combined cache on the die is 50MB. High speed links allow for peak processor-to-
>>processor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s
>>
>>first thougths:
>>
>>1)total cache is 50MB so 6MB L3 is likely
>>2)ring-based system interface (reminds me original tukwila aka Tanglewood)
>>3) 8 cores (no surprise here) multi(treaded) means more than two (more likely four)
>>4) four engineers are from Fort Collins and three from Hudson
>>
>>now could be nice if David, Paul or anyone else would grab something from the designers before february...
>>
>
>The only problem with that estimate is that would mean the L2 cache would go from
>independent I and D on Montecito/Montvale/Tukwila back to shared ID with 256KB
>capacity. That's a significant reduction from 1MB+256KB on Montecito/Montvale and 512KB+256KB on Tukwila.
Yeah, I'd say it's a lot more likely that the L3 cache is 4-5MB per core.
As was pointed out, you need your directory cache (2-4MB), your L2D caches (2-4MB), your L2I caches (4-8MB). So I'd guess that each core has 6MB of SRAM total...with the directory cache using up the rest. That leaves around 4-4.5MB of L3 cache, presuming that they use 1MB L2I + 256KB L2D.
David