Ivy Bridge and stacked DRAM

By: Jouni Osmala (josmala.delete@this.cc.hut.fi), January 4, 2011 12:39 am
Room: Moderated Discussions
>>LPDDR2 caps out at 533/1066. That crawls compared to DDR3. Then again, if you wanted
>>to devote the die area and power to it, you could easily slap 4GB of 'slow' LPDDR2
>>at 2048b width under the lid of a Westmere/Haswell-EX. Would you give up 1MB of
>>L3 for that (picking die tradeoffs out of thin air)? How about 2MB?
>>
>>On a $5000 server chip, why the )#$(*# not?
>
>Latency is the important issue, you're quoting bandwidths.

That issue can be mitigated, by having the tags on processor die and running tag check parallel to L3 tag check, so no latency penalty if not hit, and slight improvement on L4 cache hit. But bandwidth is useful when considering number of cores that are going to be in the high end server processors in couple of years there is real potential for situation that things that used to be latency sensitive become bandwidth sensitive because there just isn't enough main memory bandwidth to feed all cores.
Putting tags on processor would limit the maximum size of the cache for given line width. And you cannot increase it much because of moving those lines between processors also take package pins.
So for cache applications they probably would need some full custom low latency memory on package. However Intel employs enough software engineers and Linux has good enough market share in servers that they just could use it like a special main memory. No they wouldn't rewrite every application just part of a kernel and couple of libraries. Simply put the thread specific stuff on same package as the processor that runs it on by the threading library.
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TopicPosted ByDate
Ivy Bridge and stacked DRAMDavid Kanter2010/12/29 02:06 PM
  Ivy Bridge and stacked DRAMGroo2010/12/29 04:31 PM
    Ivy Bridge and stacked DRAMRohit2010/12/30 12:02 AM
      Ivy Bridge and stacked DRAMGroo2010/12/30 01:20 PM
    Ivy Bridge and stacked DRAManon2010/12/30 03:26 AM
      Ivy Bridge and stacked DRAMGroo2010/12/30 01:23 PM
        Ivy Bridge and stacked DRAManon2010/12/30 03:59 PM
          Ivy Bridge and stacked DRAMGroo2010/12/30 07:24 PM
            64 bit LPDDR2 is enough for Ivy's 24EU IGP...Hans de Vries2010/12/30 11:54 PM
              64 bit LPDDR2 is enough for Ivy's 24EU IGP...Groo2011/01/01 01:07 PM
                64 bit LPDDR2 is enough for Ivy's 24EU IGP...Hans de Vries2011/01/07 06:27 PM
              64 bit LPDDR2 is enough for Ivy's 24EU IGP...IntelUser20002011/01/03 05:28 AM
          Ivy Bridge and stacked DRAMJouni Osmala2011/01/04 12:39 AM
        Ivy Bridge and stacked DRAManon2010/12/30 03:59 PM
  Ivy Bridge and stacked DRAMEuronymous2010/12/29 10:35 PM
    TSV + interposerDavid Kanter2010/12/29 11:36 PM
      TSV + interposerEuronymous2010/12/30 06:25 AM
      TSV + interposerarf2010/12/30 12:11 PM
        TSV dimensions vs. metal layersDavid Kanter2010/12/30 12:33 PM
          TSV dimensions vs. metal layersarf2010/12/30 03:24 PM
            TSV dimensions vs. metal layersDavid Kanter2010/12/30 06:10 PM
        TSV + interposerGroo2010/12/30 02:08 PM
          TSV + interposerDavid Kanter2010/12/30 02:45 PM
            TSV + interposerGroo2010/12/30 07:22 PM
    Ivy Bridge and stacked DRAMGroo2010/12/30 01:26 PM
  Ivy Bridge and stacked DRAMajensen2010/12/30 03:50 AM
  512-bit without TSV?M.Isobe2010/12/30 06:47 AM
    Multiple interposers are needed for ultra-wide interfaceM.Isobe2010/12/30 07:12 AM
  Stacked DRAM: Good for what it is intendedWill Smith2011/01/03 05:37 AM
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