TSV + interposer

By: David Kanter (dkanter.delete@this.realworldtech.com), December 29, 2010 11:36 pm
Room: Moderated Discussions
Euronymous (euronymous@realworldtech.com) on 12/29/10 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 12/29/10 wrote:
>---------------------------
>>According to our friend Charlie, Ivy Bridge will have LPDDR2 stacked to provide
>>a low latency and high bandwidth DRAM close to the CPU/GPU. This should significantly
>>boost performance and lower power:
>>
>>http://www.semiaccurate.com/2010/12/29/intel-puts-gpu-memory-ivy-bridge/
>>
>>The interesting question is whether this is dedicated for the GPU, or for both CPU and GPU.
>>
>>David

Hey - Good to see you again!

>I imagine this is provided as just a cache and not acting >like a main memory.

I think that's the case. It sounds to me like they might have a separate memory controller for this. I certainly don't think that Intel will ever want to have a 512b wide memory controller.

>Though is it stacked at the IC layer, or is it merely >package level integration?

I'm pretty sure Charlie is referring to TSVs that are routed through a silicon interposer (for stability/production). I think this is probably more of a packaging level technique. I'm pretty sure the advantages of separate test/verification for each piece of silicon outweighs the advantages of greater integration (at this point) for really high volumes.

David
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TopicPosted ByDate
Ivy Bridge and stacked DRAMDavid Kanter2010/12/29 02:06 PM
  Ivy Bridge and stacked DRAMGroo2010/12/29 04:31 PM
    Ivy Bridge and stacked DRAMRohit2010/12/30 12:02 AM
      Ivy Bridge and stacked DRAMGroo2010/12/30 01:20 PM
    Ivy Bridge and stacked DRAManon2010/12/30 03:26 AM
      Ivy Bridge and stacked DRAMGroo2010/12/30 01:23 PM
        Ivy Bridge and stacked DRAManon2010/12/30 03:59 PM
          Ivy Bridge and stacked DRAMGroo2010/12/30 07:24 PM
            64 bit LPDDR2 is enough for Ivy's 24EU IGP...Hans de Vries2010/12/30 11:54 PM
              64 bit LPDDR2 is enough for Ivy's 24EU IGP...Groo2011/01/01 01:07 PM
                64 bit LPDDR2 is enough for Ivy's 24EU IGP...Hans de Vries2011/01/07 06:27 PM
              64 bit LPDDR2 is enough for Ivy's 24EU IGP...IntelUser20002011/01/03 05:28 AM
          Ivy Bridge and stacked DRAMJouni Osmala2011/01/04 12:39 AM
        Ivy Bridge and stacked DRAManon2010/12/30 03:59 PM
  Ivy Bridge and stacked DRAMEuronymous2010/12/29 10:35 PM
    TSV + interposerDavid Kanter2010/12/29 11:36 PM
      TSV + interposerEuronymous2010/12/30 06:25 AM
      TSV + interposerarf2010/12/30 12:11 PM
        TSV dimensions vs. metal layersDavid Kanter2010/12/30 12:33 PM
          TSV dimensions vs. metal layersarf2010/12/30 03:24 PM
            TSV dimensions vs. metal layersDavid Kanter2010/12/30 06:10 PM
        TSV + interposerGroo2010/12/30 02:08 PM
          TSV + interposerDavid Kanter2010/12/30 02:45 PM
            TSV + interposerGroo2010/12/30 07:22 PM
    Ivy Bridge and stacked DRAMGroo2010/12/30 01:26 PM
  Ivy Bridge and stacked DRAMajensen2010/12/30 03:50 AM
  512-bit without TSV?M.Isobe2010/12/30 06:47 AM
    Multiple interposers are needed for ultra-wide interfaceM.Isobe2010/12/30 07:12 AM
  Stacked DRAM: Good for what it is intendedWill Smith2011/01/03 05:37 AM
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