Stacked DRAM: Good for what it is intended

By: Will Smith (will.smith.insights.delete@this.gmail.com), January 3, 2011 5:37 am
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 12/29/10 wrote:
---------------------------
>According to our friend Charlie, Ivy Bridge will have LPDDR2 stacked to provide
>a low latency and high bandwidth DRAM close to the CPU/GPU. This should significantly
>boost performance and lower power: [...]

This makes perfect sense from my point of view.

_This_ in the present context means: Put all graphics memory in same package as uP.

_This_ in the present context does NOT mean: Add cache or main memory to the uP package.

Reasons:
1) A Si-interposer is dirt cheap. It's probably quite a bit lower cost than [sum of] packaging the DRAM stack, plus test the packaged stack, plus solder it on the board, plus board space and board routing including test, plus using a DIMM with associated connector if required.
2) The need for number of graphics bytes is relatively small (compared to main memory). One Gig is plenty for ALL applications for which an integrated graphics is sufficient. And I mean ALL. I can even imagine that a version with half of that memory could see the light of day as well. I hope we agree that for the enthusiasts, a dedicated graphics chip is what is needed, so the discussion of stacked graphics DRAM on uP is void for those few cases.
3) TSV DRAM stacks are in the ramping phase - fast. Intel does NOT use a custom made = expensive DRAM, they only have to use pre-manufactured, standard, ultra high volume DRAM stacks. Thanks to standardization with a growing number of suppliers to choose from (= pressure price down for Intel). This keeps costs very low. By avoiding a complicated bank/rank multi-drop bus via 'going wide', bandwidth can be optimally exploited (but not latency).

Summary so far ==> Extremely good choice for systems where integrated graphics is sufficient. Pumps all the profit to Intel's pockets. Good choice! However, to avoid confusion, this is purely a cost play, not a performance play in my point of view.

4) I don't see the benefit of using the same approach for main memory -> There is simply not sufficient memory - and even more important, there is not enough choice (=variants) for the customer.
==> Not good for main memory.
Note: I'm speaking of a mid-range PC, not of a mobile device or low-end PC. For mid-range PC's, on-package DRAM technology will be ready by ca 2012/13 when 4GB (or 2GB +2GB)DDR3 stacks might become widespread. By that time, I could well imagine that first mid-range PC's have all memory on-package, going to >50% by 2015. If a company has such uP-GPU-main-and-graphics-memory package integration technology under control, they will own the low-end market near term and mid-range PC marked mid-term, as nothing else will be cost competitive! Side remark: Will the ARM camp be in that position by 2012/13 or 2015 respectively? What about the Atom roadmap? Can AMD keep up with that? They have the GPU, but do they have the memory? Or will this push AMD to where they belong (the high-end)?

5) For cache, even Si-interposer attached DRAM is too far away. The latency is not keeping up with what would be needed.
==> Not good for cache memory either.
Note: For cache use, a DRAM chip would have to be TSV-stacked with the processor, on top or below the uP. This either means holes in the uP if the uP is at the bottom (uP chip designers really freak out when thinking about a possible hole in the middle of e.g. the FPU unit or 2nd level cache array), or it means custom = expensive DRAM chip underneath the uP chip with tons of holes for signal and power vias from uP to package (DRAM chip designers will tell you to go right out of the door when you ask them to leave room in their large memory arrays for several thousand uP signal/power holes).

Finally - I don't get it yet why this should be lower power compared to an equivalent board level attached configuration. The DRAM works exactly the same, and the drivers are exactly the same. So where is the power saved? Is it because the same configuration (with wide bus) can not be implemented on-board?

Best regards,
Will
< Previous Post in Thread 
TopicPosted ByDate
Ivy Bridge and stacked DRAMDavid Kanter2010/12/29 02:06 PM
  Ivy Bridge and stacked DRAMGroo2010/12/29 04:31 PM
    Ivy Bridge and stacked DRAMRohit2010/12/30 12:02 AM
      Ivy Bridge and stacked DRAMGroo2010/12/30 01:20 PM
    Ivy Bridge and stacked DRAManon2010/12/30 03:26 AM
      Ivy Bridge and stacked DRAMGroo2010/12/30 01:23 PM
        Ivy Bridge and stacked DRAManon2010/12/30 03:59 PM
          Ivy Bridge and stacked DRAMGroo2010/12/30 07:24 PM
            64 bit LPDDR2 is enough for Ivy's 24EU IGP...Hans de Vries2010/12/30 11:54 PM
              64 bit LPDDR2 is enough for Ivy's 24EU IGP...Groo2011/01/01 01:07 PM
                64 bit LPDDR2 is enough for Ivy's 24EU IGP...Hans de Vries2011/01/07 06:27 PM
              64 bit LPDDR2 is enough for Ivy's 24EU IGP...IntelUser20002011/01/03 05:28 AM
          Ivy Bridge and stacked DRAMJouni Osmala2011/01/04 12:39 AM
        Ivy Bridge and stacked DRAManon2010/12/30 03:59 PM
  Ivy Bridge and stacked DRAMEuronymous2010/12/29 10:35 PM
    TSV + interposerDavid Kanter2010/12/29 11:36 PM
      TSV + interposerEuronymous2010/12/30 06:25 AM
      TSV + interposerarf2010/12/30 12:11 PM
        TSV dimensions vs. metal layersDavid Kanter2010/12/30 12:33 PM
          TSV dimensions vs. metal layersarf2010/12/30 03:24 PM
            TSV dimensions vs. metal layersDavid Kanter2010/12/30 06:10 PM
        TSV + interposerGroo2010/12/30 02:08 PM
          TSV + interposerDavid Kanter2010/12/30 02:45 PM
            TSV + interposerGroo2010/12/30 07:22 PM
    Ivy Bridge and stacked DRAMGroo2010/12/30 01:26 PM
  Ivy Bridge and stacked DRAMajensen2010/12/30 03:50 AM
  512-bit without TSV?M.Isobe2010/12/30 06:47 AM
    Multiple interposers are needed for ultra-wide interfaceM.Isobe2010/12/30 07:12 AM
  Stacked DRAM: Good for what it is intendedWill Smith2011/01/03 05:37 AM
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