mpx (mpx@nomail.pl) on 1/23/11 wrote:
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>"Even if you don't do incoming inspection and testing / rejection of flash chips
>over 90% of memory in large arrays can have endurance which is 5x better than the
>minimum quoted figure." So 7% is just not enough! 13% found in most Sandforces
>is barely OK, while you'd really want 20-28% figure for optimal endurance.

That is quite interesting. I suspect the variation isn't quite that big for MLC flash though, because there multiple errors are expected and corrected. It's not like with SLC where one bit error more is the difference between a good and a bad block. Also the block sizes have went up a bit.

But your assumption that you need extra reserve to take advantage of this variation is wrong. If, instead of just looking at the write cycle count, the number of bit errors are taken into account when wear leveling, you get most of the benefits too. Of course counting bit errors is not all that simple.

One approach is to do the normal wear leveling by cycle count till the rated max cycle count is near, and after that to use bit error rates instead.