High-perf process: M9 = 8um thick

Natarajan, 2008 - "A 32nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171um2 SRAM Cell Size in a 291Mb Array"

Packan, 2009 - "High Performance 32nm Logic Technology Featuring 2nd Generation High-k + Metal Gate Transistors"

SOC process: M9 = 8um thick
C-H Jan, 2009 - "A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power, High Performance, and High Density Product Applications"

The reason I thought it was 7um is because I had read the following, pre-print version of the SOC paper. It claimed that M9 was 7um thick, but the official paper submitted to IEDM claims it is 8um thick (the same as the high-performance processes).

http://download.intel.com/technology/architecture-silicon/32nm/IEDM_09_32nm_SOC_abstract.pdf