Design Challenges at 22nm Article

Article: 22nm Design Challenges at ISSCC 2011
By: Dean Calver (deano.delete@this.cloudpixies.com), March 14, 2011 1:06 am
Room: Moderated Discussions
The implication that chip design will need to become more aware of the physical processes of fabrication, seems to require a change in knowledge and education base of the designers.
I wonder if that will start to bottleneck actual chip production and release schedules?

Deano
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Design Challenges at 22nm ArticleDavid Kanter2011/03/14 12:36 AM
  Design Challenges at 22nm ArticleDean Calver2011/03/14 01:06 AM
    Design Challenges at 22nm ArticleDavid Kanter2011/03/14 08:06 PM
      Design Challenges at 22nm Articlesavantu2011/03/15 04:25 AM
  Roots of this problem go way back.someone2011/03/14 06:00 AM
    EducationMoritz2011/03/15 03:42 AM
      Educationsomeone2011/03/15 06:26 AM
        EducationMoritz2011/03/15 11:44 AM
        Educationsylt2011/03/18 09:31 AM
    Roots of this problem go way back.Rob Thorpe2011/03/15 05:25 AM
      Roots of this problem go way back.someone2011/03/15 06:20 AM
        Roots of this problem go way back.Nathan Monson2011/03/15 08:17 AM
          Roots of this problem go way back.mpx2011/03/15 11:55 AM
            Roots of this problem go way back.Mark Roulo2011/03/15 01:34 PM
            Roots of this problem go way back.Rob Thorpe2011/03/15 03:42 PM
              Roots of this problem go way back.Paul2011/03/15 04:03 PM
    Roots of this problem go way back.Dean Kent2011/03/15 07:11 AM
  Design Challenges at 22nm ArticleDaniel Bizo2011/03/14 06:06 AM
    Design Challenges at 22nm ArticleLinus Torvalds2011/03/14 08:48 AM
      Design Challenges at 22nm ArticleDavid Kanter2011/03/14 08:20 PM
      Design Challenges at 22nm ArticleDean Kent2011/03/15 07:16 AM
    Design Challenges at 22nm ArticleDavid Kanter2011/03/14 09:05 AM
      Could you elaborate?Daniel Bizó2011/03/16 05:43 AM
        IDM trade offsDavid Kanter2011/03/16 09:54 AM
  Design Challenges at 22nm ArticleTianyi2012/10/17 11:24 PM
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