David Kanter (dkanter.delete@this.realworldtech.com) on March 14, 2011 1:36 am wrote:
> As Moore's Law continues, each new generation of semiconductor manufacturing is
> ushered in by new challenges, hurdles and solutions. At ISSCC 2011, a panel
> with speakers from Global Foundries, IBM, Intel, Renesas and TSMC discussed
> manufacturing and circuit design interactions at the upcoming 22nm node.
> Industry leaders have reached a broad technical consensus, although with several
> subtle differences. This report explores the key challenges and solutions at
> 22nm; focusing on variation and co-optimization between design and
> manufacturing. As a result of the needed collaboration, understanding of
> physical design and manufacturing is even more critical to cutting edge chip
> development and achieving good performance, power and yields.
>
> t="_blank">http://www.realworldtech.com/page.cfm?ArticleID=RWT031411013528
>
> As
> always, comments and feedback are welcome.
>
> David

Hi, David

I am doing researches on process variations. What's your opinion on this issue for 22nm technology? Is it still an important factor that manufacturers should take into consideration? I read another paper called "process technology variation", it mentioned systematic and random variations can be reduced by new innovations such as new transistor architectures. Do you think this can solve the process variation problems and do we need techniques at OS level to deal with "process variation" (Such as mapping and scheduling algorithms) ?

Thanks,

Tianyi