Vincent Diepeveen (diep@xs4all.nl) on 4/20/11 wrote:
---------------------------
>Heikki Kultala (hkultala@iki.NOSPAM.fi) on 4/20/11 wrote:
>---------------------------
>>>It's simple. It's 3072 cores @ 0.88Ghz versus nvidia 448 cores @ 1.2Ghz. 3072 cores
>>>always win by factor 3-4 then or so.
>>>
>>>No discussions there.
>>
>>Wrong.
>>
>>It's 24 ATI cores per chip versus 28-32 nvidia cores per chip.
>>
>>And, it's 384 ATI SPMD lanes per chip versus 448-512 nvidia SPMD lanes per chip.
>>
>>VLIW ALU != core
>
>I wrote it in popular language, but that doesn't stop idiots like you.

Says how things technically really are makes me an idiot?

>It's 3072 PE's versus 448 PE's.

Those are unit counts coming from marketting.
Those are FP ALU counts. How to feed data to those matters.

There are only 384 SPMD lanes per Cayman chip,
so one chip can execute only 384 VLIW instructions per cycle (if the program counters are correctly aligned, if not, the worst case is 24 / chip)

But, those VLIW operations can actually include 5, not 4 operations total. (but the one has to be branch, only 4 FP operations).

What makes this more complicated is how memory operations are handled.
If memory operation is being handled, no ALU operations can execute at same time on ATI. I'm not sure how this goes on nvidia, might be similar.

>What's going to be FASTER in well designed gpgpu codes?
>
>0.83Ghz * 3072 PE's is *always* going to annihilate in well designed codes a meager 448 PE's @ 1.2Ghz Tesla.

Did I say they would not? No.

I just told you are counting your cores incorrectly. And telling you are wrong seems to make me an idiot.

But if the code does not have any ILP, only parallelism between work items, then 3/4 or those ATI ALU's are idling. This practically means badly optimized code.


We cannot ignore the actual SPMD lane count. Good way is to calculate the SPMD lanes, and THEN in addition calculate that ATI can do 4-way FP VLIW on one SPMD lane, nvidia only single floating point operation.