David Kanter (dkanter@realworldtech.com) on 4/22/11 wrote:
---------------------------
>EduardoS (no@spam.com) on 4/22/11 wrote:
>---------------------------
>>David Kanter (dkanter@realworldtech.com) on 4/21/11 wrote:
>>---------------------------
>>>My understanding (http://www.realworldtech.com/page.cfm?ArticleID=RWT121410213827&p=7)
>>>is that on Cayman and Cypress, the ALUs are used for address calculations.
>>
>>As CPUs use ALUs for more complex address calculations but >we don't call "address
>>calculations" as "texture fetch", do we?
>
>I don't see your point. Some uarchs have dedicated AGUs (e.g. most x86), some
>do not (e.g. IBM, IA64).

IBM doesn't have dedicated AGUs?!? That's a new one.

IIRC only IA64 doesn't have AGUs as it has braindead simple addressing ideal for regular data/array access.

>Some ISAs only have simple addressing, which adds more
>to the dynamic instruction count - some have complex addressing and fewer instructions.
>
>In the case of AMD, they don't have dedicated AGUs. I think nvidia does, but I wouldn't swear by it.
>
>In this case, the texturing is relevant, because it means that AMD's cache is read-only. It's not a real R/W cache.
>
>>>However,
>>>initiating a texture fetch is fairly quick - most of the time is spent waiting for
>>>data.
>
>>Anh... 16 cycles each?
>
>16 cycles for what? AGEN or a texture cache read?
>
>David