Intel's 22nm Tri-Gate transistors

Article: Intel's 22nm Tri-Gate Transistors
By: Mr. Camel (a.delete@this.b.c), May 18, 2011 11:54 am
Room: Moderated Discussions
someone (someone@somewhere.com) on 5/18/11 wrote:
---------------------------
>Mr. Camel (a@b.c) on 5/18/11 wrote:
>---------------------------
>>David Kanter (dkanter@realworldtech.com) on 5/6/11 wrote:
>>---------------------------
>>>New article up:
>>>
>>>For over 40 years, the planar transistor has been the keystone of the semiconductor
>>>industry. Intel's new 22nm tri-gate transistor is revolutionary, moving transistors
>>>into a three dimensional world. After 10 years of research, this novel structure
>>>is the next step for Moore's Law and promises to substantially improve performance and power efficiency.
>>>
>>>http://www.realworldtech.com/page.cfm?ArticleID=RWT050511195446
>>>
>>>Enjoy,
>>>
>>>
>>>David
>>Intel stated that the layout engineers could increase transistor drive current
>>(and therefore transistor performance) by placing multiple fins between the source and drain.
>>
>>Now, Intel stated that at higher voltages they are seeing an 18% performance gain
>>w.r.t. 32 nm. Does this 18% improvement apply to a single fin transistor? If so,
>>wouldn't it be reasonable to conclude that a 3 fin transistor could switch up to 54% faster than a 32 nm transistor?
>
>No, on multiple counts. First of all logic delay is a
>factor of driver drain capacitance, driver strength,
>wire load, and driven gate load as well as rise and
>fall time on the gates of the driver output stage. All of
>these are inter-related and depend on design goals
>and methodologies and emphasis can be placed
>more on one metric than others (e.g. logic speed vs
>area vs dynamic power vs logic power) depending on
>one's product needs. Secondly, one can simply make
>a 3 finger planar FET to put up against a 3 fin 3DFET.
>It all comes down to transistor transconductance per
>unit area. Intel has not disclosed design rules and
>electrical parameters for 3DFET and planar processes
>made with equivalent feature size to allow that kind of
>comparison to be made.
>
>It appears that Intel's 3DFET process can pack more
>transistor ooomph per square micron than an equivalent
>planar process but how much more is uncertain. Also
>keep in mind since about 350 nm or so microprocessor
>frequency has been determined by where the curve of
>frequency vs core voltage intersects the power budget
>rather than simply the fastest possible circuit operation
>at the process maximum supply voltage. It is here that
>the 3DFET process appears to be a huge win.

Thanks.

So based on what you are saying, it is impossible to predict what Ivy Bridge's top frequency bin will be at launch, right?

The run of the mill tech enthusiast sites are predicting that Ivy Bridge will come out at 20% higher frequencies than current top end Sandy Bridge products - so about 4 GHz. But they are saying this purely based on Intel's statement that the 22 nm transistors are approx. 20% faster at the upper end of the voltage range. So are they full of BS?
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TopicPosted ByDate
Intel's 22nm Tri-Gate transistorsDavid Kanter2011/05/06 12:27 AM
  Intel's 22nm Tri-Gate transistorsa reader2011/05/06 08:42 AM
  Intel's 22nm Tri-Gate transistorssomeone2011/05/06 10:56 AM
    Intel's 22nm Tri-Gate transistorsDavid Kanter2011/05/06 11:30 AM
      tick-tockDaniel Bizo2011/05/06 02:06 PM
        tick-tockjoset2011/05/06 04:22 PM
          tick-tockanon2011/05/06 04:30 PM
            tick-tockjoset2011/05/06 05:20 PM
              tick-tockanon2011/05/06 09:08 PM
              tick-tockhobold2011/05/07 03:15 PM
                tick-tockIntelUser20002011/05/07 03:20 PM
                22nm - all 3D, all the timeDavid Kanter2011/05/08 01:08 PM
                  22nm - all 3D, all the timeRaf2011/05/09 09:41 AM
          tick-tockArcadian2011/05/07 02:07 PM
            tick-tockjoset2011/05/07 07:18 PM
              tick-tockDan Downs2011/05/08 05:22 AM
                tick-tockjoset2011/05/08 07:08 PM
                  tick-tockJouni Osmala2011/05/08 08:09 PM
                    tick-tockmere mortal2011/05/09 03:53 AM
                      i didn't understood, you may be right, thanks. :) (NT)Daniel Bizo2011/05/09 09:13 AM
                      tick-tockjoset2011/05/09 04:28 PM
                        tick-tockDan Downs2011/05/09 06:45 PM
                          tick-tockjoset2011/05/09 08:31 PM
          tick-tockJack2011/05/12 05:20 PM
            tick-tockjoset2011/05/13 06:48 PM
  Intel's 22nm Tri-Gate transistorsHans de Vries2011/05/08 06:33 PM
    FD-SOIDavid Kanter2011/05/08 07:29 PM
      FD-SOIHans de Vries2011/05/08 09:06 PM
        FD-SOIDavid Kanter2011/05/08 11:57 PM
    Intel's 22nm Tri-Gate transistorsAaron Spink2011/05/08 09:48 PM
    interview with finfet+fd-soi inventorjokerman2011/05/09 10:51 PM
  Intel's 22nm Tri-Gate transistorsajensen2011/05/09 09:13 PM
  As big as they make it?Erik2011/05/10 11:26 AM
    As big as they make it?David Kanter2011/05/10 03:17 PM
      As big as they make it?gruehunter2011/05/10 05:43 PM
        As big as they make it?David Kanter2011/05/10 06:53 PM
    As big as they make it?ajensen2011/05/10 10:58 PM
    As big as they make it? me: yesMoritz2011/05/11 11:20 PM
  Intel's 22nm Tri-Gate transistorsMr. Camel2011/05/18 07:41 AM
    Intel's 22nm Tri-Gate transistorssomeone2011/05/18 10:00 AM
      Intel's 22nm Tri-Gate transistorsMr. Camel2011/05/18 11:54 AM
        Intel's 22nm Tri-Gate transistorssomeone2011/05/18 03:10 PM
          Intel's 22nm Tri-Gate transistorsDaniel Bizo2011/05/19 03:59 AM
            Intel's 22nm Tri-Gate transistorssomeone2011/05/19 06:17 AM
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