Partial update seems kind of odd

Article: Why Apple Won’t ARM the MacBook
By: rwessel (robertwessel.delete@this.yahoo.com), May 10, 2011 9:57 pm
Room: Moderated Discussions
anonymous42 (no@thanks.com) on 5/10/11 wrote:
---------------------------
>Wilco (Wilco.Dijkstra@ntlworld.com) on 5/10/11 wrote:
>---------------------------
>>Finally the flag-less scheme has difficulty providing >overflow/carry detection and multi-word add/subtract.
>
>A flag-less CELL SPU has cg (carry generate) and bg (borrow generate) instructions,
>what place 1 in LSB if carry was generated.
>It is very easy way and nice way.


Out of curiosity...

Not being familiar with Cell SPUs, do they also provide a three-input add and subtract (and carry generate) instructions? Because just being able to generate a carry is only half the battle - without a good way to use it, multi-word arithmetic stays clumsy if you have to generate more than the first carry, and you'd end up with something like:

;r1 = carry in, out
;r2,r3 = current words of operands
;r4 = sum out

add r4,r2,r3
cg r5,r2,r3
cg r6,r4,r1
add r4,r4,r1
or r1,r5,r6

While that is (sometimes) better than the sequences usually* used to generate carries without ISA support, it’s not a huge improvement.


*For an add, if you compare the sum with either of the operands, and it’s lower, you have a carry. On some RISCs, that’s essentially an ordinary compare_unsigned_less_than instruction, on others the result of the compare has to be cooked a bit to end up as a bit in register.
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