Condition register uses

Article: Why Apple Won’t ARM the MacBook
By: Paul A. Clayton (paaronclayton.delete@this.gmail.com), May 10, 2011 5:56 pm
Room: Moderated Discussions
Exophase (exophase@gmail.com) on 5/10/11 wrote:
---------------------------
[snip]
>Personally I never really liked the 4-flag model to begin with and would have preferred
>a MIPS like flags-less model with "set" instructions (make predication work with
>say, 3 registers), or possibly an SH-like model with one flag whose update depends on the instruction used.

I tend to favor something closer to the Power Architecture--
multiple (8 for Power) 4-bit condition registers. One
advantage of such is that it allows SIMD compares to
include settings for matching none, one, some, all. (That is
probably mainly an instruction encoding advantage--not
needing larger compare instructions.) With multiple
condition registers it is possible to have different classes
of instructions set different registers implicitly or
explicitly (or even always set one register). Four bit
size seems like a decent trade-off between address/name
size and data size.

In theory, one could also set multiple conditions early such
that at most one full branch mispredition penalty would be
paid. In some cases, it might be possible to load a 4-bit
condition register with four bits of a flag to accelerate
some control flow. (Even with predictable branches, early
resolution of branches could have some advantages.)

I also like having Architected state match semantic state,
i.e., it seems more wasteful to use 32 bits to encode one
bit than to use four bits. Having explicitly small values
could have some advantages for forwarding as well as for
storage (the storage factor could be an advantage if one
wanted to provide a future file in the front end--yes it
would be possible to have a future file with the most
significant bit, least significant bit (for Alpha), and
zero condition, but it might be less desirable to hold
multiple full registers to allow for persistent conditions).

By the way, MIPS FP uses condition codes set by comparison
operations for branches.

This seems to be an area where a clear consensus has not
yet developed. (Most of the old arguments against
condition codes are based on the model in which most
instructions always set the singular condition code.)

It is a little disappointing to me that only a single carry
bit is usually provided. It seems that it would be possible
to provide four carry bits with the input selected by two
bits of one of the source register names and the output
selected by two bits of the destination register name.
Such might even work somewhat well with a RAT.
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                Partial update seems kind of oddExophase2011/05/10 08:51 AM
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