Jonathan Kang (johnbk@gmail.com) on 6/22/11 wrote:
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>One thing to note is that around 45nm and below, a temperature inversion effect
>occurs where going below 0C (peak performance is actually around ~15C or so) actually increases circuit delay.
>
>In fact, at 28nm, gate-delay is worse at -30C than it is at 125C.
>
>This is due to the dominance of surface inversion effects -- which raises threshold
>voltage -- at low-drain currents, which happens to correlate with smaller feature sizes.

Isn't that only an issue at low voltages when you have few carriers? Won't overclockers be at high enough voltages that temperature inversion doesn't matter?