By: Mark Roulo (nothanks.delete@this.xxx.com), August 15, 2011 3:30 pm
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 8/10/11 wrote:
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>AFAIK, Intel has not exposed any shared memory to SW, which is required for OpenCL.
>They could use the L3 cache for shared memory, but the performance seems like it
>would be pretty awful due to high latency.
Shared memory is a logical, not physical, concept in a cache-coherent system. The L1 would probably wind up being used for typical OpenCL codes (the mapping being one nVidia SM -> 1 x86 core).
>I also wonder about numerical accuracy.
Do we expect x86 numerics to be *WORSE* than GPU numerics?
>It's also possible that OpenCL is feasible, but has such abhorrent performance
>that they judged it better to simply wait for the next generation.
My expectation is that OpenCL performance on x86 is a *long* way from being performance competitive with hand coded SSE/AVX intrinsics. Intel's marketing question would be, "Is there a large enough market for performance willing to code in OpenCL, but unwilling to use intrinsics?"
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>AFAIK, Intel has not exposed any shared memory to SW, which is required for OpenCL.
>They could use the L3 cache for shared memory, but the performance seems like it
>would be pretty awful due to high latency.
Shared memory is a logical, not physical, concept in a cache-coherent system. The L1 would probably wind up being used for typical OpenCL codes (the mapping being one nVidia SM -> 1 x86 core).
>I also wonder about numerical accuracy.
Do we expect x86 numerics to be *WORSE* than GPU numerics?
>It's also possible that OpenCL is feasible, but has such abhorrent performance
>that they judged it better to simply wait for the next generation.
My expectation is that OpenCL performance on x86 is a *long* way from being performance competitive with hand coded SSE/AVX intrinsics. Intel's marketing question would be, "Is there a large enough market for performance willing to code in OpenCL, but unwilling to use intrinsics?"
