Article: Llano Hot Chips Update

Article: Llano at Hot Chips
By: Gionatan Danti (g.danti.delete@this.assyoma.it), September 1, 2011 3:01 am
Room: Moderated Discussions
iz (i@z.x) on 9/1/11 wrote:
---------------------------
>David Kanter (dkanter@realworldtech.com) on 8/31/11 wrote:
>---------------------------
>>As always, we encourage feedback and discussions.
>
>The article mentions:
>
>A large frequency range is essential for the DVFS and good performance for consumer
>products. However it is undesirable for the frequency to be very coarse-grained
>without smaller intermediate steps. In many lightly loaded scenarios the CPU cores
>will often switch back to the base frequency to keep under the power and thermal
>limits. These frequency adjustments cost both performance and power, so it is better
>to have a variety of steady state frequencies available and avoid transitions. For
>example, 5-10% frequency steps would yield much better results.
>

>
>But I don't think that is actually very true. Looking at
>my laptop, which has fine grained control between 600MHz
>and 1400MHz, the cpu ends up at 1400MHz for 22% and at 600
>for 77%. CPU loads are very spiky in nature. The transition
>latencies are low enough that a 50% CPU load looks like an
>alternating sequence of 0% and 100% CPU loads.
>
>Only thing that makes sense for fine grained frequency
>control is when the CPU does it automatically when waiting
>for memory to catch up. But OS/BIOS-level frequency control
>has no use for fine grained intermediate steps, because
>going straight to max speed and back to sleep saves more
>power and has better performance. Power saving between
>different frequency steps is too small and the latencies
>for changing between the steps too high to keep up with
>the machine load.
>
>The only useful case I can think of is when a lot of IO
>is happening which doesn't need much CPU processing time,
>but causes interrupts often enough that going to sleep
>would add too much latency. Or other, more predictable
>steady-state loads. But those seem likely to show up at
>server loads.
>

This is true. In fact, this Anandtech article prove just that: http://www.anandtech.com/show/2919/8

On the other hand, to have more choice is (almost) always a good thing. For example, there can be some workload were the CPU is supposed to finish a task in a fixem amount of time, but no before (eg: video frames deconding). In this case, the CPU should be able to use some more intermediate state.

In a perfect world where CPU wake time/power cost is nearly zero, I think that the best thing is to let the CPU to run to maximim clock and simply to poweroff itself when not used. However, in the real world on/off transitions are time and power expensive and so intermediate states can have its use.

So I think that David is right in its claims.

Regards.
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TopicPosted ByDate
Article: Llano Hot Chips UpdateDavid Kanter2011/08/31 12:32 PM
  Article: Llano Hot Chips UpdateMS2011/08/31 01:22 PM
    Article: Llano Hot Chips UpdateDavid Kanter2011/08/31 06:07 PM
      Article: Llano Hot Chips UpdateMS2011/09/01 08:16 AM
        Article: Llano Hot Chips UpdateDavid Kanter2011/09/01 01:52 PM
    Article: Llano Hot Chips UpdateGionatan Danti2011/09/01 02:53 AM
      Links are okDavid Kanter2011/09/01 04:02 AM
  Article: Llano Hot Chips Updateiz2011/09/01 02:07 AM
    Article: Llano Hot Chips UpdateGionatan Danti2011/09/01 03:01 AM
    Article: Llano Hot Chips UpdateDavid Kanter2011/09/01 04:08 AM
      Article: Llano Hot Chips Updateiz2011/09/02 01:04 AM
  Article: Llano Hot Chips Updateiz2011/09/01 02:08 AM
  More fusion, how?Moritz2011/09/04 12:33 AM
    More fusion, how?Rohit2011/09/04 09:27 AM
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