Article: AMD's Mobile Strategy
By: Exophase (exophase.delete@this.gmail.com), December 16, 2011 2:33 pm
Room: Moderated Discussions
If you actually stop and look at the P6 uop decode ratios you'll see they're almost as bad as Netburst. All you referred to was uop ratios "in the past", which, without further citation, is liable to be x86 at its worst. Without anyhing to counter that it's most suitable to take it as such. Since you don't offer the counter with P6 I'm not going to - if you want that argument to be pushed forward do it yourself. And a lot of those things I've listed are anything but "rarely used" operations. Like calls and returns, increments and decrements, sub-32 bit loads, multiplies, pushes, pops, and increments/decrements. Seriously? Yeah. Whatever. I chose a selection of operations I think are significant, and without DATA you calling them anything but is your take vs mine: and by the way, your word is not as all-encompassing as you think it is.
Since I know you won't show the very BASIC courtesy to do so here are the figures for P6:
store: 2 uops (this is seriously the friggin silver bullet against your "uops = RISC" argument, please tell me the RISC uarch that takes two cycles for stores)
push: 3 uops
pops: 2 uops
imul: 1 uop
all branches: 1 uop, but 2 cycles
indirect call: 4 uops
shift/rotate by variable: 3 uops
inc/dec: 1 uop
adc/sbb: 2 uops
setcc: 1 uop
cmov: 2 uops
So it doesn't have the grievous inc/dec/mul/setcc penalty but it has its own problems. Of course ARM can do all of these in one cycle and of course that means ARMv7 or ARM64, pick as you please.
If you want people to not bring up figures from the past don't use them to try to make a point. Period. At the very least show the courtesy to cite SOMETHING when bringing up figures like your "1.2 to 1.7" one. Or if you later abstain on it have the common courtesy to admit you were too hasty.
I agree absolutely that different ISAs offer different semantics and expressiveness, and I've made it pretty clear that I have no illusions against this.. But you offer that x86 is better than a particular ISA (ARMv7a or ARM64) with nothing more than illuminating x86's advantages and ignoring ARM's. And that's a waste of everyone's time.
I recognize x86's strengths and I especially recognize the accomplishments of Intel's micro-architectures. I also recognize its weaknesses, which you seem oblivious to. That doesn't mean I'm Wilco, that doesn't mean I'm "blathering", that doesn't mean any of your pejoratives or mindless insults or the least bit warranted. Stop being such an x86 apologetic. Just stop. God knows it doesn't need your endorsement. And please, maybe for once in your life try "that's a good point" instead of "you're a fucking idiot."
Since I know you won't show the very BASIC courtesy to do so here are the figures for P6:
store: 2 uops (this is seriously the friggin silver bullet against your "uops = RISC" argument, please tell me the RISC uarch that takes two cycles for stores)
push: 3 uops
pops: 2 uops
imul: 1 uop
all branches: 1 uop, but 2 cycles
indirect call: 4 uops
shift/rotate by variable: 3 uops
inc/dec: 1 uop
adc/sbb: 2 uops
setcc: 1 uop
cmov: 2 uops
So it doesn't have the grievous inc/dec/mul/setcc penalty but it has its own problems. Of course ARM can do all of these in one cycle and of course that means ARMv7 or ARM64, pick as you please.
If you want people to not bring up figures from the past don't use them to try to make a point. Period. At the very least show the courtesy to cite SOMETHING when bringing up figures like your "1.2 to 1.7" one. Or if you later abstain on it have the common courtesy to admit you were too hasty.
I agree absolutely that different ISAs offer different semantics and expressiveness, and I've made it pretty clear that I have no illusions against this.. But you offer that x86 is better than a particular ISA (ARMv7a or ARM64) with nothing more than illuminating x86's advantages and ignoring ARM's. And that's a waste of everyone's time.
I recognize x86's strengths and I especially recognize the accomplishments of Intel's micro-architectures. I also recognize its weaknesses, which you seem oblivious to. That doesn't mean I'm Wilco, that doesn't mean I'm "blathering", that doesn't mean any of your pejoratives or mindless insults or the least bit warranted. Stop being such an x86 apologetic. Just stop. God knows it doesn't need your endorsement. And please, maybe for once in your life try "that's a good point" instead of "you're a fucking idiot."