Article: AMD's Mobile Strategy
By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), December 17, 2011 6:45 am
Room: Moderated Discussions
Linus Torvalds (torvalds@linux-foundation.org) on 12/16/11 wrote:
---------------------------
>Here is, for comparison,
>a rather interesting POWER comparison with a more modern
>Intel CPU (Woodcrest), which shows very close to 1.0:
>
>http://lca.ece.utexas.edu/pubs/spec09_ciji.pdf
>>
>
>which is also interesting because their pathlengths are
>actually very comparable with POWER. It is possible (in
>fact likely) that at least part of that is simply
>differences in compilers too, of course.
Very interesting paper indeed! So POWER and x86 have the same instruction counts on average across Spec when going all out for performance. It's even more compelling due to using very different compilers, so you can't blame it on using identical code generation strategies.
I can certainly try to get numbers to confirm this for ARM as well, but I think the paper says it all: RISC and CISC nowadays have very similar instruction complexity - in part because CISCs stopped using complex instructions and RISC instructions became more complex.
So can we now agree 1 ARM decoder = 1 x86 decoder?
Wilco
---------------------------
>Here is, for comparison,
>a rather interesting POWER comparison with a more modern
>Intel CPU (Woodcrest), which shows very close to 1.0:
>
>http://lca.ece.utexas.edu/pubs/spec09_ciji.pdf
>>
>
>which is also interesting because their pathlengths are
>actually very comparable with POWER. It is possible (in
>fact likely) that at least part of that is simply
>differences in compilers too, of course.
Very interesting paper indeed! So POWER and x86 have the same instruction counts on average across Spec when going all out for performance. It's even more compelling due to using very different compilers, so you can't blame it on using identical code generation strategies.
I can certainly try to get numbers to confirm this for ARM as well, but I think the paper says it all: RISC and CISC nowadays have very similar instruction complexity - in part because CISCs stopped using complex instructions and RISC instructions became more complex.
So can we now agree 1 ARM decoder = 1 x86 decoder?
Wilco