Article: AMD's Mobile Strategy
By: none (none.delete@this.none.com), December 17, 2011 5:00 pm
Room: Moderated Discussions
David Kanter (dkanter@realworldtech.com) on 12/17/11 wrote:
---------------------------
[...]
>Second, if you look at GCC, nearly 30% of the instructions are 'complex' (i.e.
>using uop fusion or macro-op fusion).
Yes. OTOH the total instructions required to complete gcc is
very close to the one required on POWER5. I'll refrain from
drawing any conclusion on that, but it looks like at the ISA
level the expressiveness of POWER5 is similar to IA32.
I wonder why they didn't target 64-bit x86 for gcc, as the low
number of registers might have meant more instructions for
spilling.
---------------------------
[...]
>Second, if you look at GCC, nearly 30% of the instructions are 'complex' (i.e.
>using uop fusion or macro-op fusion).
Yes. OTOH the total instructions required to complete gcc is
very close to the one required on POWER5. I'll refrain from
drawing any conclusion on that, but it looks like at the ISA
level the expressiveness of POWER5 is similar to IA32.
I wonder why they didn't target 64-bit x86 for gcc, as the low
number of registers might have meant more instructions for
spilling.
