Article: AMD's Mobile Strategy
By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), December 17, 2011 5:29 pm
Room: Moderated Discussions
none (none@none.com) on 12/17/11 wrote:
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>David Kanter (dkanter@realworldtech.com) on 12/17/11 wrote:
>---------------------------
>[...]
>>Second, if you look at GCC, nearly 30% of the instructions are 'complex' (i.e.
>>using uop fusion or macro-op fusion).
>
>Yes. OTOH the total instructions required to complete gcc is
>very close to the one required on POWER5. I'll refrain from
>drawing any conclusion on that, but it looks like at the ISA
>level the expressiveness of POWER5 is similar to IA32.
>
>I wonder why they didn't target 64-bit x86 for gcc, as the low
>number of registers might have meant more instructions for
>spilling.
The paper explains they used the fastest version, and clearly GCC would be faster in 32-bit mode due to being very pointer intensive. Using 32-bit pointers in 64-bit mode would be better (actual Spec submissions use special options for that).
Wilco
---------------------------
>David Kanter (dkanter@realworldtech.com) on 12/17/11 wrote:
>---------------------------
>[...]
>>Second, if you look at GCC, nearly 30% of the instructions are 'complex' (i.e.
>>using uop fusion or macro-op fusion).
>
>Yes. OTOH the total instructions required to complete gcc is
>very close to the one required on POWER5. I'll refrain from
>drawing any conclusion on that, but it looks like at the ISA
>level the expressiveness of POWER5 is similar to IA32.
>
>I wonder why they didn't target 64-bit x86 for gcc, as the low
>number of registers might have meant more instructions for
>spilling.
The paper explains they used the fastest version, and clearly GCC would be faster in 32-bit mode due to being very pointer intensive. Using 32-bit pointers in 64-bit mode would be better (actual Spec submissions use special options for that).
Wilco
