Exophase (exophase@gmail.com) on 12/20/11 wrote:
>
>The thing is, we're not talking about "RISC" here, we're talking specifically about
>ARM. ARM can do all of those things as one instruction, and its loads and stores
>have very competent addressing.

ARM doesn't have anywhere near the kinds of address
generation that x86 has.

The whole "base+small offset/shifted index" is just a tiny
part of the equation. Static addresses are common, and are
part of that "x86 has much more flexible immediates" that
you dismissed so cavalierly.

Big PC-relative offsets and larger immediates are a big
part of address generation. And things like thread-local
storage is actually important too these days.

You do realize that even the oft-maligned x86 segmenting
is actually used again? Using a segment for thread-
local storage is actually nice. Having access to it from
a CISC instruction set in a single instruction also has
real threading advantages, because you have the hardware
giving atomicity guarantees wrt NMI's and other events,
even in user space.

So there really are advantages to the x86 instruction set.
In the kernel, we do a lot of per-cpu things, because
we care about scalability more than the average bear, and
it's a real advantage how we can do a per-cpu increment
with a single instruction, exactly because that way we do
not need to disable interrupts or preemption.

And part of that is the read-modify-write ops, but part of
it is also the addressing modes: using a segment prefix to
cause the operation to go to the percpu area.

So some memory op issues cause x86 instructions to be
much more powerful, because it has secondary
effects.

Linus