Exophase (exophase@gmail.com) on 12/20/11 wrote:
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>http://board.flatassembler.net/topic.php?p=137802

I'm looking through this right now.
Looks like most immediates are limited to 12-bit. Some are 9-bit signed.

There is also a special load immediate form (MOVK) that splices a 16-bit chunk into a register, so you can construct a 64-bit constant in 4 instructions.

The most interesting addressing modes are a 12-bit displacement mode
Load dest = [base + imm12]
and "register offset" which is
Load dest = [base + index << scale]

Compare to x86's SIB mode
Load dest = [base + index << scale + imm64]

The ARM64 version has more choices of scale.

The x86 version combines not only the AGU op and Load, but also up to 1 ALU op, and the loading and adding in of a full-length immediate.

So for example, the x86-64 instruction
ADD RAX, [RBX + RSI + imm64]

would expand to a six instruction ARM64 counterpart something like this:
MOVZ X1, imm16
MOVK X1, imm16, 16
MOVK X1, imm16, 32
MOVK X1, imm16, 48
LDR X1, [X1, X3]
ADD X2, X1, X2


Also there's this:
"The LDM, STM, PUSH and POP instructions do not exist in A64"

So, it looks like ARM64 is RISCier than ARM32, and doesn't have much in the way of big multi-op instructions.