Article: AMD's Mobile Strategy
By: Wilco (Wilco.Dijkstra.delete@this.ntlworld.com), December 22, 2011 4:50 am
Room: Moderated Discussions
anon (anon@anon.com) on 12/21/11 wrote:
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>Wilco (Wilco.Dijkstra@ntlworld.com) on 12/21/11 wrote:
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>>Exophase (exophase@gmail.com) on 12/21/11 wrote:
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>>>stubar (nothanks@gmail.com) on 12/21/11 wrote:
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>>>>I've always done small to large. Is there a technical reason for large to small?
>>>
>>>If you go large to small you're guaranteed to stay aligned without padding.
>>
>>You still get the same amount of tail padding.
>>
>>Wilco
>
>That is a pretty archaic way to lay out a data structure. It should be grouped
>according to cache line access locality, type, and of false sharing with other CPUs,
>etc. Unless you're not using caches or something crazy.
Most structs are much smaller than a cache line. If you're thinking about big descriptors like used by OSes then you would indeed layout differently.
Wilco
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>Wilco (Wilco.Dijkstra@ntlworld.com) on 12/21/11 wrote:
>---------------------------
>>Exophase (exophase@gmail.com) on 12/21/11 wrote:
>>---------------------------
>>>stubar (nothanks@gmail.com) on 12/21/11 wrote:
>>>---------------------------
>>>>I've always done small to large. Is there a technical reason for large to small?
>>>
>>>If you go large to small you're guaranteed to stay aligned without padding.
>>
>>You still get the same amount of tail padding.
>>
>>Wilco
>
>That is a pretty archaic way to lay out a data structure. It should be grouped
>according to cache line access locality, type, and of false sharing with other CPUs,
>etc. Unless you're not using caches or something crazy.
Most structs are much smaller than a cache line. If you're thinking about big descriptors like used by OSes then you would indeed layout differently.
Wilco