Article: AMD's Mobile Strategy
By: John Yates (john.delete@this.yates-sheets.org), December 26, 2011 10:46 am
Room: Moderated Discussions
mpx (mpx@nomail.pl) on 12/21/11 wrote:
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>This does not justify x86 variable lenght encoding. It could be used to argue for
>2^n multiples encoding (eg. 32-bit &64-bit per instruction).
It is possible to find a middle ground between radically variable length instruction schemes and rigid single size.
In the mid-80s I designed the instruction set for Apollo Computer's DN10K, a response to SUN's introduction of the SPARC architecture. I had previously used the:
- PDP-8: all instructions were 12 bits
- PDP-11: instruction were 16, 32 or 48 bits
- VAX: made the x86 encoding look simple
My earliest ISA proposals had RISCy instruction semantics within a variable length encoding, slightly more complex than the PDP-11. After repeated proposals of that ilk Rich Barh[1], the lead architect, explained to me why my suggestions were being so poorly received. He said "John, I cannot imagine attending a computer architecture conference, standing up in front of my peers, stating that Apollo set out to design a modern RISC architecture and ended up with a variable length scheme."
In time I came to see fixed size instructions as really a means to an end. The end is minimal pipeline stages ahead of issue, simple decode and simple issue. To that list Apollo added parallel issue. The design we ended up building[2] had 2 instruction sizes: 32 bits and 64 bits. 64 bit instructions were required to be naturally aligned in the instruction stream. The instruction length was specified by a single bit.
Though not really VLIW the DN10K could have been termed a "Moderately Wide Instruction Word" machine. Every cycle it could issue:
- one integer, branch or memory reference instruction
- optionally, one floating point instruction
The floating point instruction set include a small number of 5-operand instructions in both single and double precision. These supported a 3-operand multiply combined with either a 2-operand accumulating add or sub or a convert float to integer. When combined with a large floating point register file these instructions made the machine particularly good at running linear algebra and graphics kernels.
[1] http://www.linkedin.com/profile/view?id=308063&authType=name&authToken=03Xp&goback=%2Econ
[2] http://www.google.com/patents?id=mgkXAAAAEBAJ&pg=PA11&dq=patent+5051885&hl=en&sa=X&ei=Zar4TuaNB8KksQLOkNXXAQ&ved=0CDMQ6AEwAA
---------------------------
>This does not justify x86 variable lenght encoding. It could be used to argue for
>2^n multiples encoding (eg. 32-bit &64-bit per instruction).
It is possible to find a middle ground between radically variable length instruction schemes and rigid single size.
In the mid-80s I designed the instruction set for Apollo Computer's DN10K, a response to SUN's introduction of the SPARC architecture. I had previously used the:
- PDP-8: all instructions were 12 bits
- PDP-11: instruction were 16, 32 or 48 bits
- VAX: made the x86 encoding look simple
My earliest ISA proposals had RISCy instruction semantics within a variable length encoding, slightly more complex than the PDP-11. After repeated proposals of that ilk Rich Barh[1], the lead architect, explained to me why my suggestions were being so poorly received. He said "John, I cannot imagine attending a computer architecture conference, standing up in front of my peers, stating that Apollo set out to design a modern RISC architecture and ended up with a variable length scheme."
In time I came to see fixed size instructions as really a means to an end. The end is minimal pipeline stages ahead of issue, simple decode and simple issue. To that list Apollo added parallel issue. The design we ended up building[2] had 2 instruction sizes: 32 bits and 64 bits. 64 bit instructions were required to be naturally aligned in the instruction stream. The instruction length was specified by a single bit.
Though not really VLIW the DN10K could have been termed a "Moderately Wide Instruction Word" machine. Every cycle it could issue:
- one integer, branch or memory reference instruction
- optionally, one floating point instruction
The floating point instruction set include a small number of 5-operand instructions in both single and double precision. These supported a 3-operand multiply combined with either a 2-operand accumulating add or sub or a convert float to integer. When combined with a large floating point register file these instructions made the machine particularly good at running linear algebra and graphics kernels.
[1] http://www.linkedin.com/profile/view?id=308063&authType=name&authToken=03Xp&goback=%2Econ
[2] http://www.google.com/patents?id=mgkXAAAAEBAJ&pg=PA11&dq=patent+5051885&hl=en&sa=X&ei=Zar4TuaNB8KksQLOkNXXAQ&ved=0CDMQ6AEwAA
